CY7C1474V25-200BGC datasheet(10/38 Pages) CYPRESS

Part #	CY7C1474V25-200BGC

Description	72-Mbit (2 M 횞 36/4 M 횞 18/1 M 횞 72) Pipelined SRAM with NoBL??Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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10 / 38 page

CY7C1470V25

CY7C1472V25

CY7C1474V25

Document Number: 38-05290 Rev. *O

Page 10 of 38

Functional Overview

The

CY7C1470V25/CY7C1472V25/CY7C1474V25

are

synchronous-pipelined burst NoBL SRAMs designed specifically

to eliminate wait states during write/read transitions. All

synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock signal is qualified with the

clock enable input signal (CEN). If CEN is HIGH, the clock signal

is not recognized and all internal states are maintained. All

synchronous operations are qualified with CEN. All data outputs

pass through output registers controlled by the rising edge of the

clock. Maximum access delay from the clock rise (tCO) is 3.0 ns

(200-MHz device).

Accesses can be initiated by asserting all three chip enables

(CE1, CE2, CE3) active at the rising edge of the clock. If clock

enable (CEN) is active LOW and ADV/LD is asserted LOW, the

address presented to the device will be latched. The access can

either be a read or write operation, depending on the status of

the write enable (WE). BW[x] can be used to conduct byte write

operations.

Write operations are qualified by the write enable (WE). All writes

are simplified with on-chip synchronous self-timed write circuitry.

Three synchronous chip enables (CE1, CE2, CE3) and an

asynchronous output enable (OE) simplify depth expansion. All

operations (reads, writes, and deselects) are pipelined. ADV/LD

should be driven LOW once the device has been deselected in

order to load a new address for the next operation.

Single Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,

and CE3 are all asserted active, (3) the write enable input signal

WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The

address presented to the address inputs is latched into the

address register and presented to the memory core and control

logic. The control logic determines that a read access is in

progress and allows the requested data to propagate to the input

of the output register. At the rising edge of the next clock the

requested data is allowed to propagate through the output

register and onto the data bus within 3.0 ns (200-MHz device)

provided OE is active LOW. After the first clock of the read

access the output buffers are controlled by OE and the internal

control logic. OE must be driven LOW in order for the device to

drive out the requested data. During the second clock, a

subsequent operation (read/write/deselect) can be initiated.

Deselecting the device is also pipelined. Therefore, when the

SRAM is deselected at clock rise by one of the chip enable

signals, its output will tri-state following the next clock rise.

Burst Read Accesses

The CY7C1470V25/CY7C1472V25/CY7C1474V25 have an

on-chip burst counter that allows the user the ability to supply a

single address and conduct up to four reads without reasserting

the address inputs. ADV/LD must be driven LOW in order to load

a new address into the SRAM, as described in Single Read

Accesses. The sequence of the burst counter is determined by

the MODE input signal. A LOW input on MODE selects a linear

burst mode, a HIGH selects an interleaved burst sequence. Both

burst counters use A0 and A1 in the burst sequence, and will

wrap-around when incremented sufficiently. A HIGH input on

ADV/LD will increment the internal burst counter regardless of

the state of chip enables inputs or WE. WE is latched at the

beginning of a burst cycle. Therefore, the type of access (read

or write) is maintained throughout the burst sequence.

Single Write Accesses

Write accesses are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,

and CE3 are all asserted active, and (3) the write signal WE is

asserted LOW. The address presented to the address inputs is

loaded into the address register. The write signals are latched

into the control logic block.

On the subsequent clock rise the data lines are automatically

tri-stated regardless of the state of the OE input signal. This

allows the external logic to present the data on DQ and DQP

TMS

Test mode

select

synchronous

This pin controls the test access port state machine. Sampled on the rising edge of TCK.

TCK

JTAG clock Clock input to the JTAG circuitry.

VDD

Power supply Power supply inputs to the core of the device.

VDDQ

I/O power

supply

Power supply for the I/O circuitry.

VSS

Ground

Ground for the device. Should be connected to ground of the system.

NC

–

No connects. This pin is not connected to the die.

NC/144M,

NC/288M,

NC/576M,

NC/1G

–

These pins are not connected. They will be used for expansion to the 144M, 288M, 576M and 1G

densities.

ZZ

Input-

asynchronous

ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with

data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an

internal pull-down.

Pin Definitions (continued)

Pin Name

I/O Type

Pin Description

Similar Part No. - CY7C1474V25-200BGC

Manufacturer	Part #	Datasheet	Description
Cypress Semiconductor	CY7C1474V25-200BGC	382Kb / 27P	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL??Architecture
	CY7C1474V25-200BGC	517Kb / 28P	72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
	CY7C1474V25-200BGC	878Kb / 31P	72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
	CY7C1474V25-200BGC	506Kb / 39P	72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture June 27, 2013

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CY7C1474V25-200BGC Datasheet(PDF) 10 Page - Cypress Semiconductor

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