CY7C1440AV33

Document Number: 38-05383 Rev. *K

Page 6 of 33

Pin Definitions

Name

I/O

Description

Input-

synchronous

Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK

two-bit counter.

Input-

synchronous

Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled

on the rising edge of CLK.

GW

Input-

synchronous

Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write

BWE

Input-

synchronous

Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted

LOW to conduct a byte write.

CLK

Input-

clock

Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst

counter when ADV is asserted LOW, during a burst operation.

Input-

synchronous

new external address is loaded.

Input-

synchronous

Input-

synchronous

a new external address is loaded.

OE

Input-

asynchronous

Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,

the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data

pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.

ADV

Input-

synchronous

Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it

automatically increments the address in a burst cycle.

ADSP

Input-

synchronous

Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted

LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded

into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is

ADSC

Input-

synchronous

Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted

LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded

into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.

ZZ

Input-

asynchronous

ZZ “sleep” input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”

condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ

pin has an internal pull-down.

DQs,

I/O-

synchronous

Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the

rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the

addresses presented during the previous clock rise of the read cycle. The direction of the pins is

are placed in a tri-state condition.

Power supply Power supply inputs to the core of the device.

Ground

Ground for the core of the device.

I/O ground

Ground for the I/O circuitry.

Note

1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.