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CY7C1440AV33-167AXC Datasheet(PDF) 10 Page - Cypress Semiconductor |
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CY7C1440AV33-167AXC Datasheet(HTML) 10 Page - Cypress Semiconductor |
10 / 33 page CY7C1440AV33 Document Number: 38-05383 Rev. *K Page 10 of 33 Truth Table for Read/Write The truth table for Read/Write for CY7C1440AV33 follows. [8, 9, 10] Function (CY7C1440AV33) GW BWE BWD BWC BWB BWA Read H H X X X X Read H L HH HH Write byte A – (DQA and DQPA)H L H H H L Write byte B – (DQB and DQPB)H L H H L H Write bytes B, A H L H H L L Write byte C – (DQC and DQPC)H L H L H H Write bytes C, A H L H L H L Write bytes C, B H L H L L H Write bytes C, B, A H L H L L L Write byte D – (DQD and DQPD)H L L H H H Write bytes D, A H L L H H L Write bytes D, B H L L H L H Write bytes D, B, A H L L H L L Write bytes D, C H L L L H H Write bytes D, C, A H L L L H L Write bytes D, C, B H L L L L H Write all bytes H LLL LL Write all bytes L X X X X X Notes 8. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 9. BWx represents any byte write signal. To enable any byte write BWx, a Logic LOW signal should be applied at clock rise. Any number of bye writes can be enabled at the same time for any given write. 10. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active. |
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