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CY7C136E-55JXC Datasheet(PDF) 6 Page - Cypress Semiconductor |
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CY7C136E-55JXC Datasheet(HTML) 6 Page - Cypress Semiconductor |
6 / 19 page CY7C131E, CY7C131AE CY7C136E, CY7C136AE Document Number: 001-64231 Rev. *D Page 6 of 19 Switching Characteristics Over the Operating Range Parameter [11] Description 7C131E-15/7C131AE-15 7C131E-25/7C136E-25 Unit Min Max Min Max Read Cycle tRC Read cycle time 15 –25– ns tAA Address to data valid [12] – 15–25 ns tOHA Data hold from Address change 3 –3– ns tACE CE LOW to data valid [12] – 15–25 ns tDOE OE LOW to data valid [12] – 10–15 ns tLZOE OE LOW to Low Z [13, 14, 15] 3 –3– ns tHZOE OE HIGH to High Z [13, 14, 15] – 10–15 ns tLZCE CE LOW to Low Z [13, 14, 15] 3 –5– ns tHZCE CE HIGH to High Z [13, 14, 15] – 10–15 ns tPU CE LOW to power-up [13] 0 –0– ns tPD CE HIGH to power-down [13] – 15–25 ns Write Cycle [16] tWC Write cycle time 15 –25– ns tSCE CE LOW to write end 12 –20– ns tAW Address setup to write end 12 –20– ns tHA Address hold from write end 0 –0– ns tSA Address setup to write start 0 –0– ns tPWE R/W pulse width 10 –12– ns tSD Data setup to write end 10 –15– ns tHD Data hold from write end 0 –0– ns tHZWE [13] R/W LOW to High Z [15] – 10–15 ns tLZWE [13] R/W HIGH to Low Z [15] 3 –3– ns Notes 11. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V and output loading of the specified IOL/IOH, and 30 pF load capacitance. 12. AC Test Conditions use VOH = 1.6 V and VOL = 1.4 V. 13. This parameter is guaranteed but not tested. 14. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 15. Parameters tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tested with CL = 5 pF as in part (c) of Figure 3 on page 5. Transition is measured ±500 mV from steady state voltage. 16. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be low to initiate a write and either signal can terminate |
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