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CY7C0832BV-133AI Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY7C0832BV-133AI Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 31 page  CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833V FLEx18™ 3.3 V 128 K / 256 K / 512 K × 18 Synchronous Dual-Port RAM Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-06059 Rev. *W Revised October 13, 2011 FLEx18™ 3.3 V 128 K / 256 K / 512 K × 18 Synchronous Dual-Port RAM Features ■ True dual-ported memory cells that allow simultaneous access of the same memory location ■ Synchronous pipelined operation ■ Family of 2-Mbit, 4-Mbit, and 9-Mbit devices ■ Pipelined output mode allows fast operation ■ 0.18 micron CMOS for optimum speed and power ■ High speed clock to data access ■ 3.3 V low power ❐ Active as low as 225 mA (typ) ❐ Standby as low as 55 mA (typ) ■ Mailbox function for message passing ■ Global master reset ■ Separate byte enables on both ports ■ Commercial and Industrial temperature ranges ■ IEEE 1149.1 compatible JTAG boundary scan ■ 144-ball FBGA (13 mm × 13 mm) (1.0 mm pitch) ■ 120-pin TQFP (14 mm × 14 mm × 1.4 mm) ■ Pb-free packages available ■ Counter wrap around control ❐ Internal mask register controls counter wrap around ❐ Counter-interrupt flags to indicate wrap around ❐ Memory block retransmit operation ■ Counter readback on address lines ■ Mask register readback on address lines ■ Dual chip enables on both ports for easy depth expansion Functional Description The FLEx18™ family includes 2-Mbit, 4-Mbit, and 9-Mbit pipelined, synchronous, true dual port static RAMs that are high speed, low power 3.3 V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal setup and hold time. During a Read operation, data is registered for decreased cycle time. Each port contains a burst counter on the input address register. After externally loading the counter with the initial address, the counter increments the address internally (more details to follow). The internal Write pulse width is independent of the duration of the R/W input signal. The internal Write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle powers down the internal circuitry to reduce the static power consumption. One cycle with chip enables asserted is required to reactivate the outputs. Additional features include: readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap around, counter interrupt (CNTINT) flags, readback of mask register value on address lines, retransmit functionality, interrupt flags for message passing, JTAG for boundary scan, and asynchronous Master Reset (MRST). The CY7C0833V device in this family has limited features. See Address Counter and Mask Register Operations on page 7 for details. Product Selection Guide Density 2 Mbit (128 K × 18) 4 Mbit (256 K × 18) 9 Mbit (512 K × 18) Part Number CY7C0831AV CY7C0832AV CY7C0832BV [1] CY7C0833V Maximum Speed (MHz) 133 167 133 100 Maximum Access Time - Clock to Data (ns) 4.0 4.0 4.4 4.7 Typical Operating Current (mA) 225 225 225 270 Package 120-pin TQFP 120-pin TQFP 120-pin TQFP 144-ball FBGA Note 1. CY7C0832AV and CY7C0832BV are functionally identical. |
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Similar Description - CY7C0832BV-133AI |
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