CY7C130, CY7C130A

CY7C131, CY7C131A

1 K × 8 Dual-Port Static RAM

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

•

408-943-2600

Document Number: 38-06002 Rev. *H

Revised October 12, 2011

1 K × 8 Dual-Port Static RAM

Features

reads of the same memory location

bus width to 16 or more bits using slave CY7C140/CY7C141

input on CY7C140/CY7C141

52-pin TQFP

Functional Description

The CY7C130/130A/CY7C131/131A/CY7C140[1] and CY7C141

are high speed CMOS 1 K by 8 dual-port static RAMs. Two ports

are provided permitting independent access to any location in

memory. The CY7C130/130A/CY7C131/131A can be used as

either a standalone 8-bit dual-port static RAM or as a master

dual-port RAM in conjunction with the CY7C140/CY7C141 slave

dual-port device in systems requiring 16-bit or greater word

widths. It is the solution to applications requiring shared or

buffered data, such as cache memory for DSP, bit-slice, or multi-

processor designs.

Each port has independent control pins; chip enable (CE), write

enable (R/W), and output enable (OE). Two flags are provided

on each port, BUSY and INT. BUSY signals that the port is trying

to access the same location currently being accessed by the

other port. INT is an interrupt flag indicating that data is placed

in a unique location (3FF for the left port and 3FE for the right

port).

An

automatic

power

down

feature

is

controlled

independently on each port by the chip enable (CE) pins.

The CY7C130/130A and CY7C140 are available in 48-pin DIP.

The CY7C131/131A and CY7C141 are available in 52-pin

PLCC, 52-pin Pb-free PLCC, 52-pin PQFP, and 52-pin Pb-free

PQFP.

ARBITRATION

LOGIC

(7C130/7C131 ONLY)

AND

INTERRUPT LOGIC

CONTROL

I/O

CONTROL

I/O

MEMORY

ARRAY

ADDRESS

DECODER

ADDRESS

DECODER

[2]

[3]

[3]

Logic Block Diagram

Notes

1. CY7C130 and CY7C130A are functionally identical; CY7C131 and CY7C131A are functionally identical.

2. CY7C130/130A/CY7C131/131A (Master): BUSY is open drain output and requires pull-up resistor.

CY7C140/CY7C141 (Slave): BUSY is input.

3. Open drain outputs: pull-up resistor required.