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MCM69P817ZP2.5R Datasheet(PDF) 8 Page - Motorola, Inc |
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MCM69P817ZP2.5R Datasheet(HTML) 8 Page - Motorola, Inc |
8 / 16 page MCM69P817 8 MOTOROLA FAST SRAM AC OPERATING CONDITIONS AND CHARACTERISTICS (3.6 V ≥ VDD ≥ 3.135 V, 70°C ≥ TA ≥ 0°C, Unless Otherwise Noted) Input Timing Measurement Reference Level 1.5 V . . . . . . . . . . . . . . . Input Pulse Levels 0 to 3.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Slew Rate (See Figure 3) 1.0 V/ns . . . . . . . . . . . . . . . . . . . . . . . . Output Timing Reference Level 1.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . Output Load See Figure 2 Unless Otherwise Noted . . . . . . . . . . . . . . Output Rise/Fall Times (Max) 2.0 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . READ/WRITE CYCLE TIMING (See Notes 1 and 2) P Sb l MCM69P817–2.5 200 MHz MCM69P817–3 180 MHz MCM69P817–3.5 166 MHz Ui N Parameter Symbol Min Max Min Max Min Max Unit Notes Cycle Time tKHKH 5 — 5.5 — 6 — ns Clock High Pulse Width tKHKL 2.2 — 2.5 — 2.7 — ns 3, 4 Clock Low Pulse Width tKLKH 2.2 — 2.5 — 2.7 — ns 3, 4 Clock Access Time tKHQV — 2.5 — 3 — 3.5 ns 3 Output Enable to Output Valid tGLQV — 3.5 — 3.5 — 3.8 ns 3 Clock High to Output Active tKHQX1 0 — 0 — 0 — ns 3, 5, 6 Clock High to Output Change tKHQX2 1.5 — 1.5 — 1.5 — ns 3, 6 Output Enable to Output Active tGLQX 0 — 0 — 0 — ns 3, 5, 6 Output Disable to Q High–Z tGHQZ — 3.5 — 3.5 — 3.8 ns 3, 5, 6 Clock High to Q High–Z tKHQZ 1.5 5 1.5 5.5 1.5 6 ns 3, 5, 6 Setup Times: Address Data In Write Chip Enable ADSP, ADSC, ADV tADKH tDVKH tWVKH tEVKH tADSKH 0.5 0.5 0.5 0.5 1.5 — 0.5 0.5 0.5 0.5 1.5 — 0.5 0.5 0.5 0.5 1.5 — ns 3 Hold Times: Address ADSP, ADSC, ADV Data In Write Chip Enable tKHAX tKHADSX tKHDX tKHWX tKHEX 1.0 — 1.0 — 1.0 — ns 3 NOTES: 1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high and SE3 low whenever ADSP or ADSC is asserted. 2. All read and write cycle timings are referenced from K or G. 3. Tested per AC Test Load, Figure 2. 4. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels. 5. Measured at ± 200 mV from steady state. 6. This parameter is sampled and not 100% tested. |
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