 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
CY7C006A-20JXC Datasheet(PDF) 9 Page - Cypress Semiconductor |
|
||||||||||||||||||||||||||||||
CY7C006A-20JXC Datasheet(HTML) 9 Page - Cypress Semiconductor |
|
|
9 / 22 page  CY7C006A/CY7C007A CY7C016A/CY7C017A Document Number: 38-06045 Rev. *F Page 9 of 22 Switching Characteristics Over the Operating Range[14] Parameter Description CY7C006A CY7C007A CY7C016A CY7C017A Unit –12[15] –15 –20 Min Max Min Max Min Max READ CYCLE tRC Read Cycle Time 12 – 15 – 20 – ns tAA Address to Data Valid – 12 – 15 – 20 ns tOHA Output Hold From Address Change 3 – 3 – 3 – ns tACE[16] CE LOW to Data Valid – 12 – 15 – 20 ns tDOE OE LOW to Data Valid – 8 – 10 – 12 ns tLZOE[17, 18, 19] OE LOW to Low Z 3 – 3 – 3 – ns tHZOE[17, 18, 19] OE HIGH to High Z – 10 – 10 – 12 ns tLZCE[17, 18, 19] CE LOW to Low Z 3 – 3 – 3 – ns tHZCE[17, 18, 19] CE HIGH to High Z – 10 – 10 – 12 ns tPU[19] CE LOW to Power-Up 0 – 0 – 0 – ns tPD[19] CE HIGH to Power-Down – 12 – 15 – 20 ns WRITE CYCLE tWC Write Cycle Time 12 – 15 – 20 – ns tSCE[16] CE LOW to Write End 10 – 12 – 15 – ns tAW Address Valid to Write End 10 – 12 – 15 – ns tHA Address Hold From Write End 0 – 0 – 0 – ns tSA[16] Address Set-Up to Write Start 0 – 0 – 0 – ns tPWE Write Pulse Width 10 – 12 – 15 – ns tSD Data Set-Up to Write End 10 – 10 – 15 – ns tHD[22] Data Hold From Write End 0 – 0 – 0 – ns tHZWE[18, 19] R/W LOW to High Z – 10 – 10 – 12 ns tLZWE[18, 19] R/W HIGH to Low Z 3 – 3 – 3 – ns tWDD[20] Write Pulse to Data Delay – 25 – 30 – 45 ns tDDD[20] Write Data Valid to Read Data Valid – 20 – 25 – 30 ns BUSY TIMING[21] tBLA BUSY LOW from Address Match – 12 – 15 – 20 ns tBHA BUSY HIGH from Address Mismatch – 12 – 15 – 20 ns Notes: 14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOI/IOH and 30-pF load capacitance. 15. See page 7 for Load Conditions. 16. To access RAM, CE = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time. 17. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 18. Test conditions used are Load 3. 19. This parameter is guaranteed but not tested. 20. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 21. Test conditions used are Load 2. 22. For 15 ns industrial parts tHD Min. is 0.5 ns. [+] Feedback |
Similar Part No. - CY7C006A-20JXC |
|
Similar Description - CY7C006A-20JXC |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
