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ADS1201U1K Datasheet(PDF) 10 Page - Texas Instruments |
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ADS1201U1K Datasheet(HTML) 10 Page - Texas Instruments |
10 / 17 page 10 ADS1201 ® GAIN/OFFSET CALEN 0 1 Normal Mode 0 0 Offset Calibration, Analog inputs shorted to ground internally. 1 0 Full-Scale Calibration, Analog inputs are referenced to VREF internally. TABLE III. Calibration Enable. supply, VREF, or temperature. The amount of change which could cause a re-calibration is dependent on the application and effective resolution of the system. The results of the calibration calculations are stored in two registers in the processor chip (see Figure 1). These two calibration results can then be used to calibrate the input signal results with one of the following formulas: Equivalent Calibrated Output Code = FSC (FO1 – FO2) /(FO3 – FO2) where FO1 = Filter output code of an applied input voltage FO2 = Filter output code of the offset calibration FO3 = Filter output code of the gain calibration FSC = Desired full-scale output With a simple sinc filter, the calibrated A/D conversion would equal: Equivalent Calibrated Input Voltage = (N1 – N2) • VREF /(N3 – N2) where N1 = number of ones counted (or digital equivalent after filtering) over given time (tM) with an applied input voltage N2 = number of ones counted (or digital equivalent after filtering) during offset calibration where t12 = tM N3 = number of ones counted (or digital equivalent after filtering) during gain calibration where t13 = tM A system calibration can be performed by applying two known voltage levels to the input of the converter. In this situation, the GAIN/OFFSET and CALEN pins are not used. Rather, the digital output of these two known voltages are accumulated by the processor. With this data, the processor can determine the calibration register values that are appro- priate for the application. LAYOUT CONSIDERATIONS POWER SUPPLIES The ADS1201 requires the digital supply (DVDD) to be no greater than the analog supply (AVDD). Failure to observe this condition could cause permanent damage to the ADS1201. The best scheme is to power the analog section of the design and AVDD from one +5V line and the digital section and DVDD from a separate +5V line (from the same supply). If there are separate analog and digital power supplies for the ADS1201, a good design approach would be to have the analog supply come up first, followed by the digital supply. Another approach that can be used to control the analog and digital power supply differences is shown in Figure 10. In this circuit, a connection has been made between the ADS1201 supply pins via a 10 Ω resistor. The combination of this resistor and the decoupling capacitors provides some filtering between DVDD and AVDD. The analog supply should be well regulated and low noise. For designs requiring very high resolution from the ADS1201, power supply rejection will be a concern. The requirements for the digital supply are not strict. However, high frequency noise on DVDD can capacitively couple into the analog portion of the ADS1201. This noise can originate from switching power supplies, microprocessors or digital signal processors. For either supply, high frequency noise will generally be rejected by the external digital filter at integer multiples of MCLK. Just below and above these frequencies, noise will alias back into the pass-band of the digital filter, affecting the conversion result. Inputs to the ADS1201, such as AIN, REFIN, and MCLK, should not be present before the analog and digital supplies are on. Violating this condition could cause latch-up. If these signals are present before the supplies are on, series resistors should be used to limit the input current. If one supply must be used to power the ADS1201, the system’s analog supply should be used to power both AVDD and DVDD. Experimentation may be the best way to deter- mine the appropriate connection between AVDD and DVDD. GROUNDING The analog and digital sections of the design should be carefully and cleanly partitioned. Each section should have its own ground plane with no overlap between them. AGND should be connected to the analog ground plane as well as all other analog grounds. DGND should be connected to the digital ground plane and all digital signals referenced to this plane. The ADS1201 pinout is such that the converter is cleanly separated into an analog and digital portion. This should allow simple layout of the analog and digital sections of the design. For a signal converter system, AGND and DGND of the ADS1201 can be connected together. Do not join the ground planes, but connect the two with a moderate signal trace underneath the converter. For multiple converters, connect the two ground planes at one location as central to all of the converters as possible. In some cases, experimentation may be required to find the best point to connect the two planes together. Experimentation may be the best way to determine the appropriate connection between AGND and DGND. DECOUPLING Good decoupling practices should be used for the ADS1201 and for all components in the design. All decoupling capaci- tors, specifically the 0.1 µF ceramic capacitors, should be placed as close as possible to the pin being decoupled. A 1 µF and 10µF capacitor, in parallel with the 0.1µF ceramic capacitor, should be used to decouple AVDD to AGND. At a minimum, a 0.1 µF ceramic capacitor should be used to decouple DVDD to DGND, as well as for the digital supply on each digital component. |
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