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MAX11127ATI+ Datasheet(PDF) 19 Page - Maxim Integrated Products |
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MAX11127ATI+ Datasheet(HTML) 19 Page - Maxim Integrated Products |
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19 / 40 page  19 MAX11120–MAX11128 1Msps, Low-Power, Serial 12-/10-/8-Bit, 4-/8-/16-Channel ADCs Figure 2c. External Clock Timing Diagram with CHAN_ID=0 Single-Ended, Differential, and Pseudo-Differential Input The MAX11120–MAX11128 include up to 16 analog input channels that can be configured to 16 single-ended inputs, 8 fully differential pairs, or 15 pseudo-differential inputs with respect to one common input (REF-/AIN15 is the common input). The analog input range is 0V to VREF+ in single-ended and pseudo-differential mode (unipolar) and QVREF+/2 or Q VREF+ in fully differential mode (bipolar) depending on the RANGE register settings. See Table 7 for the RANGE register setting. Unipolar mode sets the differential input range from 0 to VREF+. If the positive analog input swings below the negative analog input in unipolar mode, the digital output code is zero. Selecting bipolar mode sets the differential input range to QVREF+/2 or QVREF+ depending on the RANGE register settings (Table 7). In single-ended mode, the ADC always operates in uni- polar mode. The analog inputs are internally referenced to GND with a full-scale input range from 0 to VREF+. Single-ended conversions are internally referenced to GND (Figure 3). The MAX11120–MAX11128 feature 15 pseudo differen- tial inputs by setting the PDIFF_COM bits in the Unipolar register to 1 (Table 10). The 15 analog input signals inputs are referenced to a DC signal applied to the REF-/AIN15. Fully Differential Reference (REF+, REF-) When the reference is used in fully differential mode (REFSEL = 1), the full-scale range is set by the difference between REF+ and REF-. The output clips if the input signal surpasses this reference range. ADC Transfer Function The output format of the MAX11120–MAX11128 is straight binary in unipolar mode and two’s complement in bipolar mode. The code transitions midway between successive integer LSB values, such as 0.5 LSB, 1.5 LSB. Figure 4 and Figure 5 show the unipolar and bipolar transfer func- tion, respectively. Output coding is binary, with 1 LSB = VREF+/4096. Figure 3. Equivalent Input Circuit 23 45 67 8 110111213141516 9 CS SCLK DIN DOUT 0 LSB MSB] MSB-1 MSB-2 DI[15] DI[1] 0 DI[0] DI[14] DAC COMPARATOR DAC AINn AINn+1 (GND) HOLD |
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