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MAX11120ATI+ Datasheet(PDF) 2 Page - Maxim Integrated Products |
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MAX11120ATI+ Datasheet(HTML) 2 Page - Maxim Integrated Products |
2 / 40 page 2 MAX11120–MAX11128 1Msps, Low-Power, Serial 12-/10-/8-Bit, 4-/8-/16-Channel ADCs VDD to GND.............................................................-0.3V to +4V OVDD, AIN0–AIN13, CNVST/AIN14, REF+, REF-/AIN15 to GND......................-0.3V to the lower of (VDD + 0.3V) and +4V CS, SCLK, DIN, DOUT, EOC TO GND ..... -0.3V to the Lower of (VOVDD + 0.3V) and +4V DGND to GND......................................................-0.3V to +0.3V Input/Output Current (all pins) ...........................................50mA Continuous Power Dissipation (TA = +70NC) TQFN (derate 34.4mW/NC above +70NC)..................2758mW Operating Temperature Range........................ -40NC to +125NC Junction Temperature .....................................................+150NC Storage Temperature Range............................ -65NC to +150NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow) ......................................+260NC TQFN Junction-to-Ambient Thermal Resistance (BJA)...........29NC/W Junction-to-Case Thermal Resistance (BJC)..................2NC/W ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera- tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) ELECTRICAL CHARACTERISTICS (MAX11122/MAX11125/MAX11128) (VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 1Msps, fSCLK = 16MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four- layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY (Notes 3 and 4) Resolution RES 12 bit 12 Bits Integral Nonlinearity INL ±1.0 LSB Differential Nonlinearity DNL No missing codes ±1.0 LSB Offset Error 0.7 ±2.5 LSB Gain Error (Note 5) -0.5 ±4.0 LSB Offset Error Temperature Coefficient OETC ±2 ppm/NC Gain Temperature Coefficient GETC ±0.8 ppm/NC Channel-to-Channel Offset Matching ±0.5 LSB Line Rejection PSR (Note 6) ±0.4 ±1.5 LSB/V DYNAMIC PERFORMANCE (250kHz, input sine wave) (Notes 3 and 7) Signal-to-Noise Plus Distortion SINAD 70 72.5 dB Signal-to-Noise Ratio SNR 70 72.6 dB Total Harmonic Distortion (Up to the 5th Harmonic) THD -87 -78 dB Spurious-Free Dynamic Range SFDR 79 88 dB Intermodulation Distortion IMD f1 = 249.878kHz, f2 = 219.97kHz -85 dB |
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