Part Name
         Description
F71889A

 Super Hardware Monitor + LPC I/O ( 132 Page)


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Sep, 2011
V0.21P
-38-
F71889A
7.3.2
PECI 3.0 Command and Register
PECI Configuration Register
⎯ Index 40h
Bit
Name
R/W
Default
Description
7
RDIAMSR_CMD_EN
R/W
0
When PECI temperature monitoring is enabled, set this bit 1 will
generate a RdIAMSR () command before a GetTemp () command.
6
C3_UPDATE_EN
R/W
0
If RDIAMSR_CMD_EN is not set to 1, the temperature data is not
allowed to be updated when the completion code of RdIAMSR () is
0x82.
5-4
Reserved
R
-
Reserved
3
C3_PTEMP_EN
R/W
0
Set this bit 1 to enable updateing positive value of temperature if the
completion code of RdIAMSR () is 0x82.
2
C0_PTEMP_EN
R/W
0
Set this bit 1 to enable updating positive value of temperature if the
completion code of RdIAMSR () is not 0x82 and the bit 8 of
completion code is not 1 either.
1
C3_ALL0_EN
R/W
0
Set this bit 1 to enable updating temperature value 0x0000 if the
completion code of RdIAMSR () is 0x82.
0
C0_ALL0_EN
R/W
0
Set this bit 1 to enable updating temperature value 0x0000 if the
completion code of RdIAMSR () is not 0x82 and the bit 8 of
completion code is not 1 either.
PECI Master Control Register
⎯ Index 41h
Bit
Name
R/W
Default
Description
7
PECI_CMD_START
W
-
Write 1 to this bit to start a PECI command when using as a PECI master.
(PECI_PENDING must be set to 1)
6-5
Reserved
R
-
Reserved
4
PECI_PENDING
R/W
0
Set this bit 1 to stop monitoring PECI temperature.
3
Reserved
R
-
Reserved
2-0
PECI_CMD
R/W
3’h0
PECI command to be used by PECI master.
000: PING()
001: GetDIB()
010: GetTemp()
011: RdIAMSR()
100: RdPkgConfig()
101: WrPkgConfig()
others: Reserved
PECI Master Status Register
⎯ Index 42h
Bit
Name
R/W
Default
Description
7-3
Reserved
R
-
Reserved
2
ABORT_FCS
R/WC
-
This bit is the Abort FCS status of PECI master commands. Write this bit 1
or read this byte will clear this bit to 0.
1
PECI_FCS_ERR
R/WC
-
This bit is the FCS error status of PECI master commands. Write this bit 1
or read this byte will clear this bit to 0.
0
PECI_FINISH
R/WC
-
This bit is the Command Finish status of PECI master commands. Write
this bit 1 or read this byte will clear this bit to 0.
PECI Master DATA0 Register
⎯ Index 43h
Bit
Name
R/W
Default
Description
7-0
PECI_DATA0
R/W
0
For RdIAMSR (), RdPkgConfig () and WrPkgConfig () command, this byte
represents “Host ID [7:1] & Retry [0]”. Please refer to PECI interface
specification for more detail.



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