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MM912IP812AMAF Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc

Part # MM912IP812AMAF
Description  S12P MCU and Multifunctional Ignition
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MM912IP812AMAF Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
10
Freescale Semiconductor
MM912_P812
PIN CONNECTIONS
Notes
Notes
8.
S12XEP100 signal noted for reuse of PC board for the calibration device.
MCU
64
RESET
Input
RESET
External Reset Pin
The RESET pin is an active low bidirectional control signal. It acts as an
input to initialize the MCU to a known start-up state, and an output when
an internal MCU function causes a reset. The RESET pin has an internal
pull-up device. Use external pull-up (10 k and 100 pF capacitor to
Ground) connect to the 33812 RESET pin 93.
MCU
65
VDDR
Supply
Input
VDDR
Power supply input to the internal voltage regulator. Connect to VCC and
use bypass capacitor, 100 nF to Ground.
MCU
66
VSS3
Ground
VSS3
Core Ground Pin
The voltage supply of nominally 1.8 V is derived from the internal voltage
regulator. The return current path is through the VSS3 pin. No static
external loading of these pins is permitted. Connect to Ground
MCU
67
VSSPLL
Ground
VSSPLL
PLL Ground Pin
Provides operating voltage and ground for the phased-locked loop. This
allows the supply voltage to the PLL to be bypassed independently.
Internal power and ground are generated by the internal regulator.
Connect to Ground
MCU
68
EXTAL
Clock
Input
EXTAL
Oscillator Pin
EXTAL is the external clock pin. On reset all the device clocks are
derived from the internal reference clock. Connect to external crystal and
18 pf capacitor to Ground
MCU
69
XTAL
Clock
Output
XTAL
Oscillator Pin
XTAL is the crystal driver pin. On reset all the device clocks are derived
from the internal reference clock. XTAL is the oscillator output. Connect
to external crystal and 18 pf capacitor to Ground
MCU
70
PE2
VDDPLL (9)
I/O
PLL
Supply (9)
PE2
Output of 3.3 V
regulator (9)
Port E, I/O pin 2 is a general purpose input or output pin. (Only on
S12P, not on S12XEP100)
Signals VDDPLL/VSSPLL are the secondary outputs of VREG_3V3 that
provide the power supply for the PLL and oscillator. These signals are
connected to device pins to allow external decoupling capacitors.
(100 nF...220 nF, X7R ceramic). In Shutdown mode, an external supply
driving VDDPLL/VSSPLL can replace the voltage regulator. Only on
S12XEP100 (9)
MCU
71
IRQ
I/O
PE1/IRQ
Port E, I/O pin 1 is a general purpose input pin and the maskable interrupt
request input that provides a means of applying asynchronous interrupt
requests. This will wake-up the MCU from stop or wait mode.
MCU
72
XIRQ
I/O
PE0/XIRQ
Port E, I/O pin 0 is a general purpose input pin and the non-maskable
interrupt request input that provides a means of applying asynchronous
interrupt requests. This will wake-up the MCU from stop or wait mode.
The XIRQ interrupt is level sensitive and active low. As XIRQ is level
sensitive while this pin is low, the MCU will not enter STOP mode.
Connect to 10K pull-up resistor to VCC.
MCU
73
PA1
I/O
PA1
Port A, I/O pin 1 is a general purpose input or output pin.
MCU
74
PA5
I/O
PA5
Port A, I/O pin 5 is a general purpose input or output pin.
MCU
75
PA6
VDD (9)
I/O
Supply (9)
PA6 ON S12P
Output of 3.3 V
regulator (9)
Port A, I/O pin 6 is a general purpose input or output pin. (Only on S12P,
not on S12XEP100)
Signals VDD/VSS2 are the primary outputs of VREG_3V3 that provide
the power supply for the core logic. These signals are connected to
device pins to allow external decoupling capacitors (220 nF, X7R
ceramic). In Shutdown mode, an external supply driving VDD/VSS2 can
replace the voltage regulator. Only on S12XEP100 (9)
Notes
9.
S12XEP100 signal noted for reuse of PC board for the calibration device.
Table 4. MM912_P812 Pin Definitions
Analog
or MCU
Pin
Pin Name
Pin
Function
Formal Name
Description and Recommendations


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