EDJ5308BASE-8A-E datasheet(8/130 Pages) ELPIDA

Part #	EDJ5308BASE-8A-E

Description	512M bits DDR3 SDRAM

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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EDJ5304BASE, EDJ5308BASE, EDJ5316BASE

Preliminary Data Sheet E0966E60 (Ver. 6.0)

8

Recommended DC Operating Conditions (TC = 0

°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V)

Parameter

Symbol

min.

typ.

max.

Unit

Notes

Supply voltage

VDD

1.425

1.5

1.575

V

1, 2

Supply voltage for DQ

VDDQ

1.425

1.5

1.575

V

1, 2

Input reference voltage

VREFCA (DC)

0.49

× VDDQ

0.50

× VDDQ 0.51 × VDDQ

V

3, 4

Input reference voltage for DQ

VREFDQ (DC)

0.49

× VDDQ

0.50

× VDDQ 0.51 × VDDQ

V

3, 4

Termination voltage

VTT

VDDQ/2 – TBD

TBD

VDDQ/2 + TBD

V

Notes: 1. Under all conditions VDDQ must be less than or equal to VDD.

2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.

3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than

±1% VDD (for

reference: approx

±15 mV).

4. For reference: approx. VDD/2

± 15 mV.

AC and DC Input Measurement Levels (TC = 0

°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V)

Parameter

Symbol

min.

typ.

max.

Unit

Notes

DC input logic high

VIH (DC)

VREF + 0.1

⎯

TBD

V

1

DC input logic low

VIL (DC)

TBD

⎯

VREF – 0.1

V

1

AC input logic high

VIH (AC)

VREF

+ 0.175

⎯

V

1, 2

AC input logic low

VIL (AC)

⎯

VREF – 0.175

V

1, 2

Differential input logic high

VIHdiff

+0.200

⎯

V

Differential input logic low

VILdiff

⎯

–0.200

V

Notes: 1 For DQ and DM: VREF = VREFDQ. For input only pins except /RESET; VREF = VREFCA

2. See Overshoot and Undershoot Specifications section.

Differential Input Logic Levels (TC = 0

°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V)

Parameter

Symbol

min.

max.

Unit

Note

AC differential input voltage

VID (AC)

TBD

VDDQ

+ 0.6

V

Differential input cross point voltage

relative to VDD/2

VIX

− 150

150

mV

1

AC differential cross point voltage

VOX (AC)

TBD

V

Note: 1. To guarantee tight setup and hold times as well as output skew parameters with respect to clock and

strobe, each cross point voltage of differential input signals (CK, /CK and DQS, /DQS) must meet the

requirements in table above.

The differential input cross point voltage VIX is measured from the actual cross point of true and

complement signal to the midlevel between of VDD and VSS.

VIX

CK, DQS

VDD

VDD/2

/CK, /DQS

VSS

VIX Definition

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EDJ5308BASE-8A-E Datasheet(PDF) 8 Page - Elpida Memory

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