EDD5116AFBG-5C-E datasheet(1/52 Pages) ELPIDA

Part #	EDD5116AFBG-5C-E

Description	512M bits DDR SDRAM

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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Document No. E0887E20 (Ver. 2.0)

Date Published November 2006 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2006

PRELIMINARY DATA SHEET

512M bits DDR SDRAM

EDD5108AFBG (64M words

× 8 bits)

EDD5116AFBG (32M words

× 16 bits)

Specifications

• Density: 512M bits

• Organization

 16M words × 8 bits × 4 banks (EDD5108AFBG)

 8M words × 16 bits × 4 banks (EDD5116AFBG)

• Package: 60-ball FBGA

 Lead-free (RoHS compliant)

• Power supply:

 DDR400: VDD, VDDQ = 2.6V ± 0.1V

 DDR333: VDD, VDDQ = 2.5V ± 0.2V

• Data rate: 400Mbps/333Mbps (max.)

• Four internal banks for concurrent operation

• Interface: SSTL_2

• Burst lengths (BL): 2, 4, 8

• Burst type (BT):

 Sequential (2, 4, 8)

 Interleave (2, 4, 8)

• /CAS Latency (CL): 2, 2.5, 3

• Precharge: auto precharge option for each burst

access

• Driver strength: normal/weak

• Refresh: auto-refresh, self-refresh

• Refresh cycles: 8192 cycles/64ms

 Average refresh period: 7.8µs

• Operating ambient temperature range

 TA = 0°C to +70°C

Features

• Double-data-rate architecture; two data transfers per

clock cycle

• The high-speed data transfer is realized by the 2 bits

prefetch pipelined architecture

• Bi-directional data strobe (DQS) is transmitted

/received with data for capturing data at the receiver

• Data inputs, outputs, and DM are synchronized with

DQS

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Data mask (DM) for write data

This product became EOL in April, 2010.

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EDD5116AFBG-5C-E Datasheet(PDF) 1 Page - Elpida Memory

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