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LTC3880-1 Datasheet(PDF) 10 Page - Linear Technology |
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LTC3880-1 Datasheet(HTML) 10 Page - Linear Technology |
10 / 50 page LTC3839 10 3839fa PGOOD (Pin 13): Power Good Indicator Output. This open-drain logic output is pulled to ground when the output voltage goes out of a ±7.5% window around the regulation point, after a 50μs power-bad-masking delay. Returning to the regulation point, there is a 20μs delay to power good, and a hysteresis of around 2% on both sides of the voltage window. BOOST1, BOOST2 (Pin 14, Pin 27): Boosted Floating Supplies for Top MOSFET Drivers. The (+) terminal of the bootstrap capacitor, CB, connects to this pin. The BOOST pins swing by a VIN between a diode drop below DRVCC, or (DRVCC – VD) and (VIN + DRVCC – VD). TG1, TG2 (Pin 15, Pin 26): Top Gate Driver Outputs. The TG pins drive the gates of the top N-channel power MOSFET with a voltage swing of VDRVCC between SW and BOOST. SW1, SW2 (Pin 16, Pin 25): Switch Node Connection to Inductors. Voltage swings are from a diode voltage below ground to VIN. The (–) terminal of the bootstrap capacitor, CB, connects to this node. BG1, BG2 (Pin 17, Pin 24): Bottom Gate Driver Outputs. The BG pins drive the gates of the bottom N-channel power MOSFET between PGND and DRVCC. DRVCC1, DRVCC2 (Pin 18, Pin 23): Supplies of Bottom Gate Drivers. DRVCC1 is also the output of an internal 5.3V regulator. DRVCC2 is also the output of the EXTVCC switch. Normally the two DRVCC pins are shorted together on the PCB, and decoupled to PGND with a minimum of 4.7μF ceramic capacitor, CDRVCC. VIN (Pin 19): Input Voltage Supply. The supply voltage can range from 4.5V to 38V. For increased noise immunity decouple this pin to SGND with an RC filter. Voltage at this pin is also used to adjust top gate on-time, therefore it is recommended to tie this pin to the main power input supply through an RC filter. PGND (Pin 20, Exposed Pad Pin 33): Power Ground. Connect this pin as close as practical to the source of the bottom N-channel power MOSFET, the (–) terminal of CDRVCC and the (–) terminal of CIN. Connect the exposed pad and PGND pin to SGND pin using a single PCB trace under the IC. The exposed pad must be soldered to the circuit board ground for electrical connection and rated thermal performance. INTVCC (Pin 21): Supply Input for Internal Circuitry (Not Including Gate Drivers). Normally powered from the DRVCC pins through a decoupling RC filter to SGND (typically 2Ω and 1μF). EXTVCC (Pin 22): External Power Input. When EXTVCC exceeds the switchover voltage (typically 4.6V), an internal switch connects this pin to DRVCC2 and shuts down the internal regulator so that INTVCC and gate drivers draw power from EXTVCC. The VIN pin still needs to be powered up but draws minimum current. RUN (Pin 28): Run Control Inputs. An internal propor- tional-to-absolute-temperature (PTAT) pull-up current source (~2.5μA at 25°C) is constantly connected to this pin. Taking the RUN pin below a threshold voltage (~0.8V at 25°C) shuts down all bias of INTVCC and DRVCC and places the LTC3839 into micropower shutdown mode. Allowing the RUN pin to rise above this threshold would turn on the internal bias supply and the circuitry. When the RUN pin rises above 1.2V, both channels’ TG and BG drivers are turned on and an additional 10μA temperature- independent pull-up current is connected internally to the RUN pin. The RUN pin can sink up to 100μA, or be forced no higher than 6V. VRNG (Pin 32): Current Sense Voltage Range Input. When programmed between 0.6V and 2V, the voltage applied to VRNG is twenty times (20×) the maximum sense voltage between SENSE1,2+ and SENSE1,2–, i.e., for either chan- nel, (VSENSE+ – VSENSE–) = 0.05 • VRNG. If a VRNG is tied to SGND, the channel operates with a maximum sense voltage of 30mV, equivalent to a VRNG of 0.6V; If tied to INTVCC, a maximum sense voltage of 50mV, equivalent to a VRNG of 1V. PIN FUNCTIONS |
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Similar Description - LTC3880-1 |
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