 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
LT1976 Datasheet(PDF) 8 Page - Linear Technology |
|
||||||||||||||||||||||||||||||
LT1976 Datasheet(HTML) 8 Page - Linear Technology |
|
|
8 / 30 page  LT3510 8 3510fe VIN1 (Pin 1): The VIN1 pin powers the internal control circuitry for both channels and is monitored by the undervoltage lockout comparator. The VIN1 pin is also connected to the collector of channel 1’s on-chip power NPN switch. The VIN1 pin has high dI/dt edges and must be decoupled to ground close to the pin of the device. SW1/SW2 (Pins 2, 9): The SW pin is the emitter of the on- chip power NPN. At switch off, the inductor will drive this pin below ground with a high dV/dt. An external Schottky catch diode to ground, close to the SW pin and respective VINdecouplingcapacitor’sground,mustbeusedtoprevent this pin from excessive negative voltages. IND1/IND2 (Pins 3, 8): The IND pin is the input to the on-chip sense resistor that measures current flowing in the inductor. When the current in the resistor exceeds the current dictated by the VC pin, the SW latch is held in reset, disabling the output switch. Bias current flows out of the IND pin when IND is less than 1.6V. VOUT1/VOUT2 (Pins 4, 7): The VOUT pin is the output to the on-chip sense resistor that measures current flowing in the inductor. When the current in the resistor exceeds the current dictated by the VC pin, the SW latch is held in reset, disabling the output switch. Bias current flows out of the VOUT pin when VOUT is less than 1.6V. PG1/PG2 (Pins 5, 6): The power good pin is an open-col- lector output that sinks current when the feedback falls below 90% of its nominal regulating voltage. For VIN1 above 1V, its output state remains true, although during shutdown, VIN1undervoltagelockoutorthermalshutdown, its current sink capability is reduced. The PG pins can be left open circuit or tied together to form a single power good signal. VIN2 (Pin 10): The VIN2 pin is the collector of channel 2’s on-chip power NPN switch. This pin is independent of VIN1 and may be connected to the same or a separate supply. In either case, high dI/dt edges are present and decoupling to ground must be used close to this pin. SS1/SS2 (Pins 19, 12): The SS1/2 pins control the soft- start and sequence of their respective outputs. A single capacitor from the SS pin to ground determines the outpt ramp rate. For soft-start and output tracking/sequencing details, see the Applications Information section. VC1/VC2 (Pins 18, 13): The VC pin is the output of the error amplifier and the input to the peak switch current comparator. It is normally used for frequency compensa- tion, but can also be used as a current clamp or control loop override. If the error amplifier drives VC above the maximum switch current level, a voltage clamp activates. This indicates that the output is overloaded and current is pulled from the SS pin, reducing the regulation point. FB1/FB2 (Pins 17, 14): The FB pin is the negative input to the error amplifier. The output switches regulate this pin to 0.8V, with respect to the exposed ground pad. Bias current flows out of the FB pin. SHDN (Pin 15): The shutdown pin is used to turn off both channels and control circuitry to reduce quiescent current to a typical value of 9μA. The accurate 1.28V threshold and input current hysteresis can be used as an undervoltage lockout, preventing the regulator from operating until the input voltage has reached a predetermined level. Force the SHDN pin above its threshold or let it float for normal operation. RT/SYNC (Pin 16): This RT/SYNC pin provides two modes of setting the constant switch frequency. Connecting a resistor from the RT/SYNC pin to ground will set the RT/SYNC pin to a typical value of 0.975V. The resultant switching frequency will be set by the resistor value. The minimum value of 15.4k and maximum value of 133k sets the switching frequency to 1.5MHz and 250kHz respectively. Driving the RT/SYNC pin with an external clock signal will synchronize the switch to the applied frequency. Synchro- nization occurs on the rising edge of the clock signal after PIN FUNCTIONS |
Similar Part No. - LT1976 |
|
Similar Description - LT1976 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
