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Q67100-H3757 Datasheet(PDF) 7 Page - Siemens Semiconductor Group |
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Q67100-H3757 Datasheet(HTML) 7 Page - Siemens Semiconductor Group |
7 / 26 page SLx 24C64 Semiconductor Group 7 Preliminary 1998-07-27 3 I 2C-Bus Characteristics Access to theSLx 24C64deviceisgiven viathe I 2C bus. This bidirectional bus consists of two wires SCL and SDA for clock and data. The protocol is master/slave oriented, where the serial EEPROM always takes the role of a slave. Figure 3 Bus Configuration Master Device that initiates the transfer of data and provides the clock for transmit and receive operations. Slave Device addressed by the master, capable of receiving and transmitting data. Transmitter The device using the SDA as output is defined as the transmitter. Due to the open drain characteristic of the SDA output the device applying a low level wins. Receiver The device using the SDA as input is defined as the receiver. Slave 1 Slave 2 Slave 3 Slave 4 Slave 8 Slave 5 Slave 6 Slave 7 Master VCC CC V IES02183 SCL SDA |
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