MCM67H518

2

MOTOROLA FAST SRAM

DQ0 – DQ8

CLR

Q0

Q1

A0

A1

K

ADSC

A0 – A14

E

G

ADDRESS

REGISTER

WRITE

REGISTER

ENABLE

REGISTER

DATA–IN

REGISTERS

OUTPUT

BUFFER

32K x 18

MEMORY

ARRAY

ADV

BURST LOGIC

INTERNAL

ADDRESS

A0

′

A1

′

15

9

18

15

2

A2 – A14

A1 – A0

DQ9 – DQ17

9

9

9

9

9

UW

LW

ADSP

NOTE:

All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the

next burst. When ADSP and E are sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC)

is performed using the new external address. Alternatively, an ADSP–initiated two cycle WRITE can be performed by as-

serting ADSP, E, and a valid address on the first cycle, then negating both ADSP and ADSC and asserting LW and/or UW

with valid data on the second cycle (see Single Write Cycle in WRITE CYCLES timing diagram). Note that when E and

ADSC are high, ADSP is ignored – the external address is not registered in this case.

When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent

on W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded.

After the first cycle of the burst, ADV controls subsequent burst cycles. When ADV is sampled low, the internal address

is advanced prior to the operation. When ADV is sampled high, the internal address is not advanced, thus inserting a wait

state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See

BURST SEQUENCE TABLE. Write refers to either or both byte write enables (LW, UW).

BURST SEQUENCE TABLE (See Note)

External Address

A14 – A2

A1

A0

1st Burst Address

A14 – A2

A1

A0

2nd Burst Address

A14 – A2

A1

A0

3rd Burst Address

A14 – A2

A1

A0

NOTE: The burst wraps around to its initial state upon completion.