TLV717xx

TLV717xxP

www.ti.com

SBVS176A – OCTOBER 2011 – REVISED APRIL 2012

APPLICATION INFORMATION

The TLV717xx belongs to a new family of next-generation value low-dropout (LDO) regulators. These devices

consume low quiescent current and deliver excellent line and load transient performance. These characteristics,

RF portable applications.

This family of regulators offers current foldback. Device operating junction temperature is –40°C to +125°C.

INPUT AND OUTPUT CAPACITOR REQUIREMENTS

X5R- and X7R-type ceramic capacitors are recommended because these capacitors have minimal variation in

value and equivalent series resistance (ESR) over temperature. The TLV717xx is designed to be stable with an

effective capacitance of 0.1 µF or larger at the output, though a 1-µF ceramic capacitor is recommended for

typical applications. Thus, the device is stable with capacitors of other dielectric types as well, as long as the

effective capacitance under operating bias voltage and temperature is greater than 0.1 µF. This effective

capacitance refers to the capacitance that the LDO detects under operating bias voltage and temperature

conditions; that is, the capacitance after taking both bias voltage and temperature derating into consideration. In

addition to allowing the use of cheaper dielectrics, this capability of being stable with 0.1-µF effective capacitance

also enables the use of smaller footprint capacitors that have higher derating in size- and space-constrained

applications. Note that using a 0.1-µF rated capacitor at the LDO output does not ensure stability because the

effective capacitance under the specified operating conditions would be less than 0.1 µF. Maximum ESR should

be less than 200 m

Ω.

Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-µF to

1.0-µF, low ESR capacitor across the IN and GND pins of the regulator. This capacitor counteracts reactive input

sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be

necessary if large, fast, rise-time load transients are anticipated, or if the device is not located close to the power

source. If source impedance is more than 2

Ω, a 0.1-µF input capacitor may be necessary to ensure stability.

BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE

Input and output capacitors should be placed as close to the device pins as possible. To improve ac performance

(such as PSRR, output noise, and transient response), it is recommended that the board be designed with

addition, the output capacitor ground connection should be connected directly to the device GND pin. High ESR

capacitors may degrade PSRR performance.

INTERNAL CURRENT LIMIT

The TLV717xx has an internal foldback current limit that helps to protect the regulator during fault conditions. The

current supplied by the device is gradually throttled down as the output voltage decreases. When the output is

shorted, the LDO supplies a typical current of 40 mA. Output voltage is not regulated when the device is in

much less.

The TLV717xx PMOS pass element has a built-in body diode that conducts current when the voltage at OUT

exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated,

external limiting to 5% of the rated output current is recommended.

SHUTDOWN

The enable pin (EN) is active high. The device is enabled when the voltage at the EN pin goes above 0.9 V. This

relatively lower voltage value required to turn the LDO on can be exploited to power the LDO with a GPIO of

recent processors whose GPIO logic 1 voltage level is lower than traditional microcontrollers. The device is

turned off when the EN pin is held at less than 0.4 V. When shutdown capability is not required, EN can be

connected to the IN pin.

Copyright © 2011–2012, Texas Instruments Incorporated

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Product Folder Link(s): TLV717xx TLV717xxP