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TLV62150 Datasheet(PDF) 4 Page - Texas Instruments |
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TLV62150 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 31 page 3 Exposed Thermal Pad 9 10 11 12 8 7 6 5 4 2 1 16 15 14 13 PVIN PVIN AVIN SS/TR SW SW SW PG TLV62150 SLVSB71 – FEBRUARY 2012 www.ti.com DEVICE INFORMATION RGT PACKAGE (TOP VIEW) Terminal Functions PIN(1) I/O DESCRIPTION NAME NO. SW 1,2,3 O Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and output capacitor. PG 4 O Output power good (High = VOUT ready, Low = VOUT below nominal regulation) ; open drain (requires pull-up resistor; goes high impedance, when device is switched off) FB 5 I Voltage feedback. Connect resistive voltage divider to this pin. AGND 6 Analog Ground FSW 7 I Switching Frequency Select (Low ≈ 2.5MHz, High ≈ 1.25MHz for typical operation)(2) DEF 8 I Output Voltage Scaling (Low = nominal, High = nominal + 5%)(2) Soft-Start / Tracking Pin. An external capacitor connected to this pin sets the internal voltage reference rise SS/TR 9 I time. It can be used for tracking and sequencing. AVIN 10 I Supply voltage for control circuitry. Connect to same source as PVIN. PVIN 11,12 I Supply voltage for power stage. Connect to same source as AVIN. EN 13 I Enable input (High = enabled, Low = disabled)(2) VOS 14 I Output voltage sense pin and connection for the control loop circuitry. PGND 15,16 Power ground Exposed Must be connected to AGND. Must be soldered to achieve appropriate power dissipation and mechanical Thermal Pad reliability. (1) For more information about connecting pins, see DETAILED DESCRIPTION and APPLICATION INFORMATION sections. (2) An internal pull-down resistor keeps logic level low, if pin is floating. 4 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TLV62150 |
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