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TLV717XX Datasheet(PDF) 2 Page - Texas Instruments |
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TLV717XX Datasheet(HTML) 2 Page - Texas Instruments |
2 / 23 page TLV717xx TLV717xxP SBVS176A – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION(1) PRODUCT VOUT TLV717xx(x)Pyyyz XX(X) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 475 = 4.75 V). P is optional; devices with P have an LDO regulator with an active output discharge. YYY is the package designator. Z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces). (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) At TJ = –25°C, unless otherwise noted. All voltages are with respect to GND. VALUE MIN MAX UNIT Input range, VIN –0.3 6.0 V Voltage Enable range, VEN –0.3 VIN + 0.3 V Output range, VOUT –0.3 6.0 V Current Maximum output, IOUT Internally limited Output short-circuit duration Indefinite Continuous total power dissipation, PDISS See Thermal Information table Junction range, TJ –55 +150 °C Temperature Storage junction range, Tstg –55 +150 °C Human body model (HBM) 2000 V Electrostatic discharge (ESD) ratings Charged device model (CDM) 500 V (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute- maximum rated conditions for extended periods may affect device reliability. THERMAL INFORMATION TLV717xx TLV717xxP THERMAL METRIC(1) UNITS DQN 4 PINS θJA Junction-to-ambient thermal resistance 393.3 θJC(top) Junction-to-case(top) thermal resistance 140.3 θJB Junction-to-board thermal resistance 330 °C/W ψJT Junction-to-top characterization parameter 6.5 ψJB Junction-to-board characterization parameter 329 θJC(bottom) Junction-to-case(bottom) thermal resistance 147.5 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 2 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TLV717xx TLV717xxP |
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