PD

ADR0

ADR1

DIS

SDA

SCK

2

1

3

4

5

6

17

18

16

15

14

13

8

7

9 10

11 12

23

24

22 21 20 19

BIAS

GND

VCC

COMP

MONB

MONP

ONET 1101L

24 Lead QFN

“ RGE”

ONET 1141L

24 Lead QFN

ONET1141L

www.ti.com

SLLSEB7 – MAY 2012

24 PIN QFN PACKAGE, 4mm x 4mm

(TOP VIEW)

PIN FUNCTIONS

NO.

TYPE

DESCRIPTION

PIN

NAME

1

PD

Analog

Photodiode input. Pin can source or sink current dependent on register setting.

2

ADR0

Digital-in

2-wire interface address programming pin. Leave this pad open for a default address of 0001000.

3

ADR1

Digital-in

2-wire interface address programming pin. Leave this pad open for a default address of 0001000.

4

DIS

Digital-in

Disables both bias and modulation currents when set to high state. Includes a 10k

Ω or 40kΩ pull-up

resistor to VCC. Toggle to reset a fault condition.

5

SCK

Digital-in

2-wire interface serial clock input. Includes a 10k

Ω or 40kΩ pull-up resistor to VCC.

6

SDA

Digital-in/out

2-wire interface serial data input/output. Includes a 10k

Ω or 40kΩ pull-up resistor to VCC.

7

FLT

Digital-out

Fault detection flag. High level indicates that a fault has occurred. Open drain output. Requires an

external 4.7k

Ω to 10kΩ pull-up resistor to VCC for proper operation.

8, 11, 17,

GND

Supply

Circuit ground. Exposed die pad (EP) must be grounded.

20, 23, EP

9

DIN+

Analog-in

Non-inverted data input. On-chip differentially 100

Ω terminated to DIN–. Must be AC coupled.

10

DIN–

Analog-in

Inverted data input. On-chip differentially 100

Ω terminated to DIN+. Must be AC coupled.

12

RZTC

Analog

Connect external zero TC 28.7k

Ω resistor to ground (GND). Used to generate a defined zero TC

reference current for internal DACs.

13

MONB

Analog-out

Bias current monitor. Sources a 1% replica of the bias current. Connect an external resistor to

ground (GND) to use the analog monitor (DMONB = 0). If the voltage at this pin exceeds 1.16V a

fault is triggered. Typically choose a resistor to give MONB voltage of 0.8V at the maximum desired

bias current. If the digital monitor function is used (DMONB = 1) the resistor must be removed.

14

MONP

Analog-out

Photodiode current monitor. Sources a 12.5% replica of the photodiode current when PDRNG = 1X,

a 25% replica when PDRNG = 01 and a 50% replica when PDRNG = 00. Connect an external

resistor (5k

Ω typical) to ground (GND) to use the analog monitor (DMONP = 0). If the voltage at this

pin exceeds 1.16V a fault is triggered when MONPFLT = 1. If the digital monitor function is used

(DMONP = 1) the resistor must be removed.

15

COMP

Analog

Compensation pin used to control the bandwidth of the APC loop. Connect a 0.01µF capacitor to

ground.

16

VCC

Supply

3.3V ± 10% supply voltage.

18

BIAS

Analog

Sinks or sources the bias current for the laser in both APC and open loop modes.

19, 24

VCCO

Supply

3.3V ± 10% supply voltage for the output stage.

21

OUT–

CML-out

Inverted data output.

22

OUT+

CML-out

Non-inverted data output.

Copyright © 2012, Texas Instruments Incorporated

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