OUT 1

OUT2

VCC

IN2

Pre-

drive

VCC

PWM

OCP

OCP

IN1

VSET

Integrator

DIFF

COMP

DCM

/4

ISEN

+

-

COMP

REF

ITRIP

DRV8830

SLVSAB2F

– MAY 2010 – REVISED FEBRUARY 2012

www.ti.com

FUNCTIONAL DESCRIPTION

PWM Motor Driver

The DRV8830 contains an H-bridge motor driver with PWM voltage-control circuitry with current limit circuitry. A

block diagram of the motor control circuitry is shown below.

Figure 5. Motor Control Circuitry

Bridge Control

The IN1 and IN2 control bits in the serial interface register enable the H-bridge outputs. The following table

shows the logic:

Table 2. H-Bridge Logic

IN1

IN2

OUT1

OUT2

Function

0

0

Z

Z

Standby/coast

0

1

L

H

Reverse

1

0

H

L

Forward

1

1

H

H

Brake

When both bits are zero, the output drivers are disabled and the device is placed into a low-power shutdown

state. The current limit fault condition (if present) is also cleared.

At initial power-up, the device will enter the low-power shutdown state. Note that when transitioning from either

brake or standby mode to forward or reverse, the voltage control PWM starts at zero duty cycle. The duty cycle

slowly ramps up to the commanded voltage. This can take up to 12 ms to go from standby to 100% duty cycle.

8

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© 2010–2012, Texas Instruments Incorporated

Product Folder Link(s): DRV8830