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CDCUN1208LPRHBR Datasheet(PDF) 11 Page - Texas Instruments |
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CDCUN1208LPRHBR Datasheet(HTML) 11 Page - Texas Instruments |
11 / 43 page CDCUN1208LP www.ti.com SCAS928 – MAY 2012 CLOCK OUTPUT BUFFER ELECTRICAL CHARACTERISTICS (OUTPUT MODE = LVCMOS) Unless otherwise noted, VDDOx as shown in Table sections, TA = –40°C to 85°C. ERC = Fast. For test configurations, see Figure 15 and Figure 16. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3.3V MODE fout Output frequency range 0.0008 250 MHz VDDOx = 2.97 V, IOH = –0.1 mA (All ERC Settings) 2.9 V VDDOx = 2.97 V, IOH = –5 mA (ERC = SLOW) 2.4 V VDDOx = 2.97 V, IOH = –8 mA (ERC = MED, FAST) LVCMOS High-level output VOH voltage VDDOx = 2.97 V, IOH = –6 mA (ERC = SLOW) VDDOx = 2.97 V, IOH = –10 mA (ERC = MED) 2.2 V VDDOx = 2.97 V, IOH = –12 mA (ERC = FAST) VDDOx = 2.97 V, IOL = 0.1 mA (All ERC Settings) 0.1 V VDDOx = 2.97 V, IOL = 5 mA (ERC = SLOW) 0.5 V VDDOx = 2.97 V, IOL = 8 mA (ERC = MED, FAST) LVCMOS Low-level output VOL voltage VDDOx = 2.97 V, IOL = 6 mA (ERC = SLOW) VDDOx = 2.97 V, IOL = 10 mA (ERC = MED) 0.8 V VDDOx = 2.97 V, IOL = 12 mA (ERC = FAST) VDDOx = 3.3 V, VO = 0.5 V; TA = 25°C –73 LVCMOS High-level output IOH VDDOx = 3.3 V, VO = 1.0 V; TA = 25°C –64 mA current VDDOx = 3.3 V, VO = 1.65 V; TA = 25°C –49 VDDOx = 3.3 V, VO = 2.8 V; TA = 25°C 78 LVCMOS Low-level output IOL VDDOx = 3.3 V, VO = 2.3 V; TA = 25°C 72 mA current VDDOx = 3.3 V, VO = 1.65 V; TA = 25°C 58 tPLH, tPHL Propagation Delay 5 ns ERC = Slow, 20% to 80%, fout = 100 MHz, CL = 8 pF 1.2 V/ns tSLEW-RATE Output rise/fall slew rate ERC = Medium 20% to 80%, fout = 100 MHz, CL = 8 pF 3 ERC = Fast, 20% to 80%, fout = 250 MHz, CL = 8 pF 6 tjitt-add Additive Jitter fOUT = 100 MHz, 10k-20M integration bandwidth 280 fs tsk(o) Output Skew(1) 90 ps odc Output Duty Cycle(2),(3) fOUT = 100 MHz; Pdiv = 1 45% 55% Output enable to stable clock Pin mode. fout = 100 MHz, device in active mode with tOE 2 µs output outputs disabled, OE asserted PD de-asserted to stable clock Host mode, fout = 100 MHz, device in power down mode, tPD 10 µs output PD de-asserted Time from power applied to Pin mode, fout = 100 MHz, OE asserted, measured from tPU 1 ms stable clock output(4) time VDD is valid to stable output. (1) The tsk(o) specification is only valid for equal loading with identical edge rates and output supply voltages.. (2) Assumes 50% duty cycle at the input(s) (3) odc depends on output rise and fall time (tR/tF). (4) Parameter depends significantly on power supply design and supply voltage rise time. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s) :CDCUN1208LP |
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