MCM67A618B

2

MOTOROLA FAST SRAM

BLOCK DIAGRAM

A0 – A15

DQ0 – DQ17

MEMORY ARRAY

64K x 18

E

WRITE AMP

OUTPUT

BUFFER

CONTROL

16

18

AL

LW

UW

G

16

18

18

LATCH

DL

18

9

9

LATCH

LATCH

TRUTH TABLE

E

LW

UW

AL*

DL*

G

Mode

Supply

Current

I/O

Status

H

X

X

X

X

X

Deselected Cycle

ISB

High–Z

L

X

X

L

X

X

Read or Write Using Latched Addresses

ICC

—

L

X

X

H

X

X

Read or Write Using Unlatched Addresses

ICC

—

L

H

H

X

X

L

Read Cycle

ICC

Data Out

L

H

H

X

X

H

Read Cycle

ICC

High–Z

L

L

L

X

L

X

Write Both Bytes Using Latched Data In

ICC

High–Z

L

L

L

X

H

X

Write Both Bytes Using Unlatched Data In

ICC

High–Z

L

L

H

X

X

X

Write Cycle, Lower Byte

ICC

High–Z

L

H

L

X

X

X

Write Cycle, Lower Byte

ICC

High–Z

*E and Addresses satisfy the specified setup and hold times for the falling edge of AL. Data–in satisfies the specified setup

NOTE: This truth table shows the application of each function. Combinations of these functions are valid.

Rating

Symbol

Value

Unit

Power Supply Voltage

VCC

– 0.5 to 7.0

V

Voltage Relative to VSS for Any

Pin Except VCC

Vin, Vout

– 0.5 to VCC + 0.5

V

Output Current (per I/O)

Iout

± 30

mA

Power Dissipation

PD

1.6

W

Temperature Under Bias

Tbias

– 10 to + 85

°C

Ambient Temperature

TA

0 to + 70

°C

Storage Temperature

Tstg

– 55 to + 125

°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER-

ATING CONDITIONS. Exposure to higher than recommended voltages for

extended periods of time could affect device reliability.

This device contains circuitry to protect the

inputs against damage due to high static

voltages or electric fields; however, it is advised

that normal precautions be taken to avoid

application of any voltage higher than maxi-

mum rated voltages to this high–impedance

circuit.

This BiCMOS memory circuit has been

designed to meet the dc and ac specifications

shown in the tables, after thermal equilibrium

has been established.

This device contains circuitry that will ensure

the output devices are in High–Z at power up.