Z16C3010AEC datasheet(6/102 Pages) ZILOG

Part #	Z16C3010AEC

Description	CMOS USC Universal Serial Controller

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Manufacturer	ZILOG [Zilog, Inc.]

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DS007902-0708

P R E L I M I N A R Y

Architectural Overview

Z16C30

Product Specification

2

General Description

Zilog’s Z16C30 USC Universal Serial Controller is a dual-channel multi-protocol data

communications peripheral designed for use with any conventional multiplexed or non-

multiplexed bus. The USC functions as a serial-to-parallel, parallel-to-serial converter/

controller and may be software configured to satisfy a wide variety of serial communica-

tions applications. The device contains a variety of new, sophisticated internal functions

including two baud rate generators per channel, one digital phase-locked loop (DPLL) per

channel, character counters for both receive and transmit in each channel and 32-byte data

FIFO’s for each receiver and transmitter (Figure 1 on page 3).

Zilog now offers a high speed version of the USC with improved bus bandwidth. CPU bus

accesses have been shortened from 160 ns per access to 110 ns per access. The USC has a

transmit and receive clock range of up to 10 MHz (20 MHz when using the DPLL, BRG,

or CTR) and data transfer rates as high as 10 Mbits/sec full duplex.

The USC handles asynchronous formats, synchronous byte-oriented formats such as

BISYNC, and synchronous bit-oriented formats such as HDLC. This device supports vir-

tually any serial data transfer application.

The device can generate and check CRC in any synchronous mode and can be pro-

grammed to check data integrity in various modes. The USC also has facilities for modem

controls in both channels. In applications where these controls are not needed, the modem

controls may be used for general-purpose I/O (GPIO). The same is true for most of the

other pins in each channel.

Interrupts are supported with a daisy-chain hierarchy, with the two channels having com-

pletely separate interrupt structures.

High-speed data transfers through DMA are supported by a Request/Acknowledge signal

pair for each receiver and transmitter. The device supports automatic status transfer

through DMA and also allows device initialization under DMA control.

When written to, all reserved bits must be programmed to 0.

To aid in efficiently programming the USC, support tools are available. The Technical

Manual describes in detail all features presented in this Product Specification and gives

programming sequence hints. The Programmer’s Assistant is a MS-DOS disk-based pro-

gramming initialization tool to be used in conjunction with the Technical Manual. There

are also available assorted application notes and development boards to assist in the hard-

ware/software development.

All Signals with an overline, are active Low. For example: B/W, in which WORD is active

Low, and B/W, in which BYTE is active Low.

Power connections follow these conventional descriptions:

Note:

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