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SDA5650X Datasheet(PDF) 8 Page - Siemens Semiconductor Group |
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SDA5650X Datasheet(HTML) 8 Page - Siemens Semiconductor Group |
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8 / 41 page  SDA 5650/X Semiconductor Group 8 02.97 2 System Description 2.1 Functions Referring to the functional block diagram of the PDC / VPS decoder, the composite video signal with negative going sync pulses is coupled to the pin CVBS through a capacitor which is used for clamping the bottom of the sync pulses to an internally fixed level. The signal is passed on to the slicer, an analogue circuitry separating the sync and the data parts of the CVBS signal, thus yielding the digital composite sync signal VCS and a digital data signal for further processing by comparing those signals to internally generated slicing levels. The output of the sync separator is forwarded, on one hand, to the output pin VCS, and on the other hand, to the clock generator and the timing block. The VCS signal represents a key signal that is used for deriving a system clock signal by means of a PLL and all other timing signal. The data slicer separates the data signal from the CVBS signal by comparing the video voltage to an internally generated slicing level which is found by averaging the data signal during TV line no. 16 in the VPS mode or by averaging the data signal during the clock run-in period of the teletext lines during the data entry window (DEW) in PDC mode. The clock generator delivers the system clock needed for the basic timing as well as for the regeneraton of the dataclock. It is based on two phase locked loops (PLL’s) all parts of which are integrated on chip with the exception of the loop filter components. Each of the PLL’s is composed of a voltage controlled relaxation oscillator (VCO), a phase/ frequency detector (PFD), and a charge pump which converts the digital output signals of the PFD to an analogue current. That current is transformed to a control voltage for the VCO by the off-chip loop filter. The generated VCO frequencies are 10 MHz and 13.875 MHz for VPS mode and PDC mode, respectively. All signals necessary for the control of sync and data slicing as well as for the data acquisition are generated by the Timing block. The SDA 5650 can be operated in three different modes: Depending on the selected operating mode, either teletext lines carrying 8/30 packages, the dedicated TV line no. 16 (VPS) or the teletext header bytes 38-45, 30-37, 22-29 and 14-21 are acquired. In PDC mode, only teletext rows 8/30 containing Broadcast Data Service Package (BDSP) information are acquired. The relevant bytes of 8/30 format 1 (8/30/1) and 8/30 format 2 (8/30/2) are extracted. The 8/30/1-bytes are stored in the acquisition register in a transparent way without any bit manipulation, whereas the Hamming coded bytes of packet 8/30/2 are Hamming-checked and bytes with one bit error are corrected. The storage of error free or corrected 8/30/2-data bytes in the transfer register to the I2C Bus is signalled by the DAVN output going low. |
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