SDA 5649

SDA 5649X

Semiconductor Group

49

General Information

reading from and writing to the PDC / VPS decoder is possible. The clock line SCL is controlled only

by the bus master usually being a micro controller, whereas the SDA line is controlled either by the

master or by the slave. A data transfer can only be initiated by the bus master when the bus is free,

changes state only when the SCL line is low. The only exception to that rule are the Start Condition

and the Stop Condition. Further Details are given below. The following abbreviations are used:

START :

Start Condition generated by master

AS :

Ackknowledge by slave

AM :

Ackknowledge by master

NAM :

No Ackknowledge by master

STOP :

Stop Condition generated by master

Chip Address

There are two pairs of chip addresses, which are selected by the CS0-input pin according to the

following table:

Write Mode

For writing to the PDC decoder, the following format has to be used.

Data Transfer (Write Mode)

the SDA line low while the SCL line is held high.

an acknowledge (AS) by pulling the SDA line to a low level.

CS0 Input

Write Mode

Read Mode

Low

20 (hex)

21 (hex)

High

22 (hex)

23 (hex)

START

Chipadress Write Mode

AS

Byte Set Control Register

AS

STOP