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ADSP-BF607 Datasheet(PDF) 11 Page - Analog Devices |
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ADSP-BF607 Datasheet(HTML) 11 Page - Analog Devices |
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11 / 44 page  Preliminary Technical Data Rev. PrD | Page 11 of 44 | March 2012 ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Memory Protection The Blackfin cores feature a memory protection concept, which grants data and/or instruction accesses from enabled memory regions only. A supervisor mode vs. user mode programming model supports dynamically varying access rights. Increased flexibility in memory page size options supports a simple method of static memory partitioning. System Protection All system resources and L2 memory banks can be controlled by either the processor cores, memory-to-memory DMA, or the system debug unit (SDU). A system protection unit (SPU) enables write accesses to specific resources that are locked to any of four masters: Core 0, Core 1, Memory DMA, and the Sys- tem Debug Unit. System protection is enabled in greater granularity for some modules (L2, SEC and GPIO controllers) through a global lock concept. Watchpoint Protection The primary purpose of watchpoints and hardware breakpoints is to serve emulator needs. When enabled, they signal an emula- tor event whenever user-defined system resources are accessed or a core executes from user-defined addresses. Watchdog events can be configured such that they signal the events to the other Blackfin core or to the fault management unit. Dual Watchdog The two on-chip watchdog timers each may supervise one Blackfin core. Bandwidth Monitor All DMA channels that operate in memory-to-memory mode (Memory DMA, PVP Memory Pipe DMA, PIXC DMA) are equipped with a bandwidth monitor mechanism. They can sig- nal a system event or fault when transactions tend to starve because system buses are fully loaded with higher-priority traffic. Signal Watchdogs The eight general-purpose timers feature two new modes to monitor off-chip signals. The Watchdog Period mode monitors whether external signals toggle with a period within an expected range. The Watchdog Width mode monitors whether the pulse widths of external signals are in an expected range. Both modes help to detect incorrect undesired toggling (or lack thereof) of system-level signals. Up/Down Count Mismatch Detection The up/down counter can monitor external signal pairs, such as request/grant strobes. If the edge count mismatch exceeds the expected range, the up/down counter can flag this to the proces- sor or to the fault management unit. Fault Management The fault management unit is part of the system event controller (SEC). Any system event, whether a dual-bit uncorrectable ECC error, or any peripheral status interrupt, can be defined as being a “fault”. Additionally, the system events can be defined as an interrupt to the cores. If defined as such, the SEC forwards the event to the fault management unit which may automatically reset the entire device for reboot, or simply toggle the SYS_FAULT output pins to signal off-chip hardware. Option- ally, the fault management unit can delay the action taken via a keyed sequence, to provide a final chance for the Blackfin cores to resolve the crisis and to prevent the fault action from being taken. ADDITIONAL PROCESSOR PERIPHERALS The processor contains a rich set of peripherals connected to the core via several high-bandwidth buses, providing flexibility in system configuration as well as excellent overall system perfor- mance (see the block diagram on Page 1). The processors contain high-speed serial and parallel ports, an interrupt con- troller for flexible management of interrupts from the on-chip peripherals or external sources, and power management control functions to tailor the performance and power characteristics of the processor and system to many application scenarios. The following sections describe additional peripherals that were not described in the previous sections. Timers The processor includes several timers which are described in the following sections. General-Purpose Timers There is one GP timer unit and it provides eight general-pur- pose programmable timers. Each timer has an external pin that can be configured either as a pulse width modulator (PWM) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an external clock input on the TMRx pins, an external clock TMRCLK input pin, or to the internal SCLK0. The timer units can be used in conjunction with the UARTs and the CAN controller to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. The timers can generate interrupts to the processor core, pro- viding periodic events for synchronization to either the system clock or to external signals. Timer events can also trigger other peripherals via the TRU (for instance, to signal a fault). Core Timers Each processor core also has its own dedicated timer. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generating periodic operating system interrupts. Watchdog Timers Each core includes a 32-bit timer, which may be used to imple- ment a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state, via generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer expires before |
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