XFL4020-102ME datasheet(1/40 Pages) AD

Part #	XFL4020-102ME

Description	Micro PMU with 1.2 A Buck Regulator

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Micro PMU with 1.2 A Buck Regulator

and Two 300 mA LDOs

Data Sheet

ADP5040

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother

rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

FEATURES

Input voltage range: 2.3 V to 5.5 V

One 1.2 A buck regulator

Two 300 mA LDOs

20-lead, 4 mm × 4 mm LFCSP package

Overcurrent and thermal protection

Soft start

Undervoltage lockout

Buck key specifications

Output voltage range: 0.8 V to 3.8 V

Current mode topology for excellent transient response

3 MHz operating frequency

Peak efficiency up to 96%

Uses tiny multilayer inductors and capacitors

Mode pin selects forced PWM or auto PWM/PSM modes

100% duty cycle low dropout mode

LDOs key specifications

Output voltage range: 0.8 V to 5.2 V

Low VIN from 1.7 V to 5.5 V

Stable with 2.2 µF ceramic output capacitors

High PSRR

Low output noise

Low dropout voltage

−40°C to +125°C junction temperature range

GENERAL DESCRIPTION

The ADP5040 combines one high performance buck regulator

and two low dropout regulators (LDO) in a small 20-lead

LFCSP to meet demanding performance and board space

requirements.

The high switching frequency of the buck regulator enables the use

of tiny multilayer external components and minimizes board space.

When the MODE pin is set to logic high, the buck regulator

operates in forced pulse width modulation (PWM) mode.

When the MODE pin is set to logic low, the buck regulator

operates in PWM mode when the load is around the nominal

value. When the load current falls below a predefined threshold

the regulator operates in power save mode (PSM) improving

the light-load efficiency. The low quiescent current, low

dropout voltage, and wide input voltage range of the ADP5040

LDOs extend the battery life of portable devices. The ADP5040

LDOs maintain a power supply rejection greater than 60 dB for

frequencies as high as 10 kHz while operating with a low headroom

voltage.

Each regulator in the ADP5040 is activated by a high level on

the respective enable pin. The output voltages of the regulators

are programmed though external resistor dividers to address a

variety of applications.

FUNCTIONAL BLOCK DIAGRAM

SW

C3

1µF

FB2

R4

R2

R1

R3

FB3

R3

R7

C2

2.2µF

C4

2.2µF

VOUT2

VOUT1

FB1

VIN1 = 2.3V TO

5.5V

VIN1

EN1

VIN2

EN2

EN3

VIN3

VIN3 = 1.7V

TO 5.5V

EN_LDO2

LDO2

(ANALOG)

BUCK

PGND

MODE

VOUT3

LDO1

(DIGITAL)

EN_LDO1

AVIN

RFILT = 30Ω

C5

4.7µF

VIN2 = 1.7V

TO 5.5V

VOUT1 AT

1.2A

VOUT2 AT

300mA

VOUT3 AT

300mA

C6

10µF

L1

1µH

C1

1µF

ON

OFF

ON

OFF

ON

OFF

AGND

EN_BK

PSM/PWM

FPWM

Figure 1.

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