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ADP1879ACPZ-0.3-R7 Datasheet(PDF) 6 Page - Analog Devices |
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ADP1879ACPZ-0.3-R7 Datasheet(HTML) 6 Page - Analog Devices |
6 / 40 page ADP1878/ADP1879 Data Sheet Rev. A | Page 6 of 40 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 VIN High-Side Input Voltage. Connect VIN to the drain of the high-side MOSFET. 2 COMP Output of the Error Amplifier. Connect compensation network between this pin and AGND to achieve stability (see the Compensation Network section). 3 EN IC Enable. Connect EN to VREG to enable the IC. When pulled down to AGND externally, EN disables the IC. 4 FB Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected. 5 GND Analog Ground Reference Pin of the IC. Connect all sensitive analog components to this ground plane (see the Layout Considerations section). 6 RES Current Sense Gain Resistor (External). Connect a resistor between the RES pin and GND (Pin 5). 7 VREG Internal Regulator Supply Bias Voltage for the ADP1878/ADP1879 Controller (Includes the Output Gate Drivers). Connecting a bypass capacitor of 1 μF directly from this pin to PGND and a 0.1 μF capacitor across VREG and GND are recommended. 8 SS Soft Start Input. Connect an external capacitor to GND to program the soft start period. There is a capacitance value of 10 nF for every 1 ms of soft start delay. 9 PGOOD Open-Drain Power-Good Output. PGOOD sinks current when FB is out of regulation or during thermal shutdown. Connect a 3 kΩ resistor between PGOOD and VREG. Leave PGOOD unconnected if it is not used. 10 DRVL Drive Output for the External Low-Side, N-Channel MOSFET. This pin also serves as the current sense gain setting pin (see Figure 69). 11 PGND Power Ground. Ground for the low-side gate driver and low-side N-channel MOSFET. 12 DRVH Drive Output for the External High-Side N-Channel MOSFET. 13 SW Switch Node Connection. 14 BST Bootstrap for the High-Side N-Channel MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected between VREG and BST. A capacitor from BST to SW is required. An external Schottky diode can also be connected between VREG and BST for increased gate drive capability. EP Exposed Pad. Connect the exposed pad to the analog ground pin (GND). TOP VIEW (Not to Scale) 14 13 12 11 10 9 8 6 5 4 2 3 1 7 VIN COMP EN FB GND RES VREG BST SW DRVH PGND DRVL PGOOD SS ADP1878/ADP1879 NOTES 1. CONNECT THE EXPOSED PAD TO THE ANALOG GROUND PIN (GND). |
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