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ADP1048-600-EVALZ Datasheet(PDF) 32 Page - Analog Devices

Part # ADP1048-600-EVALZ
Description  Digital Power Factor Correction Controller
Download  84 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADP1048-600-EVALZ Datasheet(HTML) 32 Page - Analog Devices

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ADP1047/ADP1048
Data Sheet
Rev. 0 | Page 32 of 84
BRIDGELESS BOOST OPERATION (ADP1048 ONLY)
During the positive ac line phase, only one boost stage is effec-
tively working. The second one is passive, and the current flows in
Q2 from the source to the drain. Turning the Q2 FET fully on
during this phase allows conduction losses in Q2 to be minimized.
The bridgeless boost configuration allows removal of the con-
duction losses caused by the input bridge of the PFC converter.
In this configuration, it is necessary to drive the two power
MOSFETs separately to achieve the highest efficiency. The
ADP1048 can provide such signals. The IBAL pin is used to
detect the ac line phase and zero crossings. Note that the maxi-
mum rating on the IBAL pin is VDD + 0.3 V; therefore, a clamp
circuit must be connected to the IBAL pin.
When the ac line phase becomes negative, the roles of Q1 and Q2
are reversed, and Q2 actively switches while Q1 is always on. The
phase information is detected from the ac line via the IBAL pin.
During the soft start phase, both FETs are switching as a precau-
tionary measure; the same happens when the phase information
on the IBAL pin becomes corrupted or inaccurate.
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
RES
RTD
ADD
SYNC
INRUSH
SCL
SDA
VAC
VFB
OVP
IBAL
ILIM
PGND
AGND
CS–
9
10
11
12
16
15
14
13
PSON
DGND
CS+
PWM2
VCORE
PWM
AC_OK
PGOOD
VDD
ADP1048
VREC
RELAY
T3
VOUT
T2
BULK
CAPACITOR
T1
Q2
Q1
T1 + T2 + T3
3.3V
PMBus
AC
INPUT
Figure 33. Schematic of Bridgeless PFC Circuit with the ADP1048
VAC
IBAL PIN
PWM
PWM2
Figure 34. Bridgeless Boost Operation


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