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NX3L2T384 Datasheet(PDF) 10 Page - NXP Semiconductors |
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NX3L2T384 Datasheet(HTML) 10 Page - NXP Semiconductors |
10 / 20 page NX3L2T384 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 7 November 2011 10 of 20 NXP Semiconductors NX3L2T384 Dual low-ohmic single-pole single-throw analog switch 12.1 Waveform and test circuits Measurement points are given in Table 10. Logic level: VOH is the typical output voltage that occurs with the output load. Fig 16. Enable and disable times 001aaj522 ten tdis switch enabled switch disabled switch disabled VX VX nY or nZ output LOW to OFF OFF to LOW nE input GND VOH VM VM GND VI Table 10. Measurement points Supply voltage Input Output VCC VM VX 1.4 V to 4.3 V 0.5VCC 0.9VOH Test data is given in Table 11. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. VEXT = External voltage for measuring switching times. Fig 17. Load circuit for switching times V VI VO 001aaj523 CL RL nY/nZ nZ/nY nE VCC VEXT = 1.5 V G Table 11. Test data Supply voltage Input Load VCC VI tr, tf CL RL 1.4 V to 4.3 V VCC 2.5ns 35pF 50 |
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