MX877

July 29, 2011

www.clare.com

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Functional Description

The MX877 is an 8 channel high voltage driver with

8-bit input control. The MX877 interfaces to a

microprocessor through a standard 3 wire serial

interface and an active-low chip select, or can be used

in a parallel-in, parallel-out configuration.

Parallel data is transferred to the I/O register of the

MX877 through the parallel input pins, IN0 through IN7

on the falling edge of the chip select pin, CS*. When

CS* is in a logic low state, serial data can be

transferred to the I/O register through the serial input

pin, SDI, and from the I/O register through the serial

output pin, SDO. Parallel or serial input data is

transferred from the I/O register to the latch and high

voltage output drivers, OUT0 through OUT7, on the

positive edge of CS*. This data remains latched until

the next positive edge of CS*.

The 8-bit I/O shift register is clocked by the serial clock

pin, SCK. Serial data presented at the SDI pin is

transferred to the shift register on the positive edge of

SCK. Data shifts out of the register through the SDO

pin on the negative edge of SCK. SDI and SCK are

ignored, and SDO transitions to a high impedance

condition when CS* is at a logic high state.

Serial data is received by the MX877 through the SDI

pin. This data is accepted on the rising edge of SCK. A

specific output is programmed to a logic high state if

SDI is at a logic high state during the rising edge of

SCK. Conversely, a specific output is programmed to a

logic low state if SDI is at a logic low state during the

rising edge of SCK. Outputs transition to their

programmed states on the positive edge of CS* if the

output enable pin, OE is in a logic high state.

The MSB input data (IN7) is presented at the serial

output pin, SDO on the falling edge of CS*. Input data

from IN6 through IN0 is sequentially presented at

SDO on negative SCK transitions if CS* remains in a

logic low state. If CS* is at a logic low state beyond 8

cycles of SCK, SDI data that has propagated through

the I/O register will then be presented at SDO. The

SDO pin transitions to a high impedance state when

CS* is in a logic level high state, thus allowing multiple

serial peripherals to share the microprocessor data

pin.

Figure 1. Serial Data Transfer Example

Devices may be serially cascaded by connecting SDO

to SDI of the next device. Pins SCK and CS* are

common to all devices in serial cascade. For

n-cascaded devices the CS* should remain low for 8n

cycles of SCK.

An output enable pin, OE enables the driver outputs

OUT0 through OUT7 when logic high. A logic low level

on OE forces the OUT0 through OUT7 outputs to a

high impedance state.

The MX877 can also operate as a parallel-in,

parallel-out level shifter and driver. SCK must remain

at a logic low state when operating in this mode.

Parallel input data presented to IN0 through IN7 is

captured on the falling edge of CS*. This data is

transferred to OUT0 through OUT7 on the rising edge

of CS*, and remains latched until the next rising edge

of CS*.

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IN7

IN6

IN5

IN4

IN3

IN2

IN1

IN0

SDI

SCK

CS

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SDO

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SDI at

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OUT7

OUT6

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OUT4

OUT3

OUT2

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