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TRF7963A Datasheet(PDF) 10 Page - Texas Instruments |
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TRF7963A Datasheet(HTML) 10 Page - Texas Instruments |
10 / 62 page TRF7963A SLOS758 – DECEMBER 2011 www.ti.com 4 Application Schematic and Layout Considerations 4.1 TRF7963A Reader System Using Parallel Microcontroller Interface 4.1.1 General Application Considerations Figure 4-1 shows the most flexible TRF7963A application. Due to the low clock frequency on the DATA_CLK line, the parallel interface is the most robust way to connect the TRF7963A with the MCU. This schematic shows matching to a 50- Ω port, which allows connection to a properly matched 50-Ω antenna circuit or RF measurement equipment (for example, a spectrum analyzer or power meter). 4.1.2 Schematic Figure 4-1 shows a sample application schematic with a parallel interface to the MCU. Figure 4-1. Application Schematic, Parallel MCU Interface The MSP430F2370 (32kB flash, 2kB RAM) is shown in Figure 4-1. Minimum MCU requirements depend on application requirements and coding style. If only one ISO protocol and/or a limited command set of a protocol must be supported, MCU flash and RAM requirements can be significantly reduced. For example, current reference firmware for ISO14443A/B (with host interface) is approximately 8kB, using 1kB RAM. An MCU that is capable of running a GPIO at 13.56 MHz is required for Direct Mode 0 operations with nonstandard transponders. 10 Application Schematic and Layout Considerations Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TRF7963A |
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