MCM6323A

9

MOTOROLA FAST SRAM

P

Sb l

MCM6323A–10

MCM6323A–12

MCM6323A–15

Ui

N

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

Notes

Write Cycle Time

tAVAV

10

—

12

—

15

—

ns

3

Address Setup Time

tAVBL

0

—

0

—

0

—

ns

Address Valid to End of Write

tAVBH

8

—

9

—

10

—

ns

Write Pulse Width

tWLWH,

tWLEH

8

—

9

—

10

—

ns

Byte Pulse Width

tBLWH,

tBLEH,

tBLBH

8

—

9

—

10

—

ns

Data Valid to End of Write

tDVBH

5

—

6

—

7

—

ns

Data Hold Time

tBHDX

0

—

0

—

0

—

ns

Write Low to Data High–Z

tWLQZ

0

4

0

5

0

6

ns

4, 5, 6

Write High to Output Active

tWHQX

3

—

3

—

3

—

ns

4, 5, 6

Write Recovery Time

tBHAX

0

—

0

—

0

—

ns

NOTES:

1. A write occurs during the overlap of E low, W low, and LB and/or UB low.

2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.

3. All write cycle timings are referenced from the last valid address to the first transitioning address.

4. Transition is measured 200 mV from steady–state voltage.

5. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.

6. This parameter is sampled and not 100% tested.

WRITE CYCLE 3

(B Controlled)

DATA VALID

tDVBH

tAVBL

tAVBH

tAVAV

tBHAX

tBLWH

tBHDX

tWLQZ

tWHQX

HIGH–Z

HIGH–Z

A (ADDRESS)

W (WRITE ENABLE)

E (CHIP ENABLE)

Q (DATA OUT)

D (DATA IN)

tBLEH

tWLWH

LB, UB (BYTE ENABLE)

tWLEH

tBLBH