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MCM63P636ZP225 Datasheet(PDF) 11 Page - Motorola, Inc |
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MCM63P636ZP225 Datasheet(HTML) 11 Page - Motorola, Inc |
11 / 27 page MCM63P636 11 MOTOROLA FAST SRAM READ/WRITE CYCLE TIMING (See Notes 1 and 2) P Sb l MCM63P636–250 MCM63P636–225 MCM63P636–200 Ui N Parameter Symbol Min Max Min Max Min Max Unit Notes Clock Cycle Time tKHKH 4 — 4.4 — 5 — ns 3, 4 Clock High Time tKH 1.06 — 1.24 — 1.46 — ns 4 Clock Low Time tKL 1.06 — 1.24 — 1.46 — ns 4 Strobe Clock Cycle Time tSKHSKH 4 — 4.4 — 5 — ns 3, 4 Strobe Clock High Time tSKH 1.06 — 1.24 — 1.46 — ns 4 Strobe Clock Low Time tSKL 1.06 — 1.24 — 1.46 — ns 4 Rising K to Rising SK tKHSKH 1.6 2.4 1.8 2.6 2.1 2.9 3 Clock Access Time tKHQV — 3.9 — 4.3 — 4.9 ns 3 Clock to Output Low–Z tKHQX 0 — 0 — 0 — ns 5, 6 Clock to Output High–Z tKHQZ — 3.9 — 4.3 — 4.9 ns 5, 6 Strobe Clock Access Time tSKHSTV — 3.9 — 4.3 — 4.9 ns 3 Setup Times: Address ADS Chip Enable Data In Data Out Write tAVKH tSVKH tEVKH tDVKH tQVSTV tWVKH 0.5 1.2 0.5 1.2 1 1.2 — 0.5 1.5 0.5 1.5 1.1 1.5 — 0.5 1.5 0.5 1.5 1.15 1.5 — ns 3 Hold Times: Address ADS Chip Enable Data In Data Out Write tKHAX tKHSX tKHEX tKHDX tSTVQX tKHWX 4 0.5 4 0.5 1 0.5 — 4.4 0.5 4.4 0.5 1.1 0.5 — 5 0.5 5 0.5 1.15 0.5 — ns 3 NOTES: 1. Reads and writes are as defined in the Truth Table. 2. All read and write cycle timings are referenced from K, SK, or data strobes. 3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels. 4. Refer to Figure 5 for input reference levels. 5. This parameter is sampled and not 100% tested. 6. Measured at ± 200 mV from steady state. VIH VIL VDDQ VSS VDDQ/2 tKH, tSKH tKL, tSKL tKHKH, tSKHSKH Figure 6. AC Timing Diagram Clock Reference |
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