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MCM6323AYJ15 Datasheet(PDF) 1 Page - Motorola, Inc |
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MCM6323AYJ15 Datasheet(HTML) 1 Page - Motorola, Inc |
1 / 12 page MCM6323A 1 MOTOROLA FAST SRAM Product Preview 64K x 16 Bit 3.3 V Asynchronous Fast Static RAM The MCM6323A is a 1,048,576 bit static random access memory organized as 65,536 words of 16 bits. Static design eliminates the need for external clocks or timing strobes; CMOS circuitry reduces power consumption and provides for greater reliability. The MCM6323A is equipped with chip enable (E), write enable (W), and output enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems. Separate byte enable controls (LB and UB) allow individual bytes to be written and read. LB controls the 8 DQa bits, while UB controls the 8 DQb bits. The MCM6323A is available in a 400 mil small–outline J–leaded (SOJ) pack- age and a 44–lead TSOP Type II package in copper leadframe for optimum printed circuit board (PCB) reliability. • Single 3.3 V ± 0.3 V Power Supply • Fast Access Time: 10, 12, 15 ns • Equal Address and Chip Enable Access Time • All Inputs and Outputs are TTL Compatible • Data Byte Control • Fully Static Operation • Power Operation: 140/135/130 mA Maximum, Active AC • Industrial Temperature Option: – 40 to + 85°C Part Number: SCM6323AYJ10A BLOCK DIAGRAM OUTPUT ENABLE BUFFER ADDRESS BUFFERS WRITE ENABLE BUFFER BYTE ENABLE BUFFER ROW DECODER COLUMN DECODER 64K x 16 BIT MEMORY ARRAY HIGH BYTE OUTPUT BUFFER 8 HIGH BYTE WRITE DRIVER LOW BYTE OUTPUT BUFFER LOW BYTE WRITE DRIVER SENSE AMPS G W LB 8 8 8 8 8 8 8 9 A CHIP ENABLE BUFFER E UB 7 HIGH BYTE OUTPUT ENABLE LOW BYTE OUTPUT ENABLE HIGH BYTE WRITE ENABLE LOW BYTE WRITE ENABLE 16 16 8 DQb 8 DQa This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. Order this document by MCM6323A/D MOTOROLA SEMICONDUCTOR TECHNICAL DATA MCM6323A YJ PACKAGE 400 MIL SOJ CASE 919–01 PIN ASSIGNMENT A Address Input . . . . . . . . . . . . . . . . . . . . . . . . E Chip Enable . . . . . . . . . . . . . . . . . . . . . . . . . W Write Enable . . . . . . . . . . . . . . . . . . . . . . . . G Output Enable . . . . . . . . . . . . . . . . . . . . . . UB Upper Byte . . . . . . . . . . . . . . . . . . . . . . . . LB Lower Byte . . . . . . . . . . . . . . . . . . . . . . . . . DQa Lower Data Input/Output . . . . . . . . . . . . DQb Upper Data Input/Output . . . . . . . . . . . . VDD + 3.3 V Power Supply . . . . . . . . . . . . . . VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . NC No Connection . . . . . . . . . . . . . . . . . . . . . PIN NAMES 5 4 3 2 1 10 9 8 7 6 11 36 37 38 39 40 41 42 35 43 44 34 E A A A A DQa DQa A VDD DQa DQa UB G A A A DQb DQb DQb VSS DQb LB 25 26 27 28 29 30 31 24 32 33 23 12 13 14 15 16 17 18 19 20 21 22 DQb DQb DQb DQb VDD A A A NC A NC W DQa DQa DQa VSS A A DQa NC A A TS PACKAGE 44–LEAD TSOP TYPE II CASE 924A–01 REV 1 10/17/97 © Motorola, Inc. 1997 |
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