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MAX17049X+T10 Datasheet(PDF) 3 Page - Maxim Integrated Products |
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MAX17049X+T10 Datasheet(HTML) 3 Page - Maxim Integrated Products |
3 / 19 page ����������������������������������������������������������������� Maxim Integrated Products 3 MAX17048/MAX17049 Micropower 1-Cell/2-Cell Li+ ModelGauge ICs Note 1: Specifications are 100% tested at TA = +25NC. Limits over the operating range are guaranteed by design and characterization. Note 2: All voltages are referenced to GND. Note 3: Test is performed on unmounted/unsoldered parts. Note 4: The voltage is trimmed and verified with 16x averaging. Note 5: This current is always present. Note 6: The IC enters shutdown mode after SCL < VIL and SDA < VIL for longer than 2.5s. Note 7: Timing must be fast enough to prevent the IC from entering sleep mode due to bus low for period >tSLEEP. Note 8: fSCL must meet the minimum clock low time plus the rise/fall times. Note 9: The maximum tHD:DAT has to be met only if the device does not stretch the low period (tLOW) of the SCL signal. Note 10: This device internally provides a hold time of at least 100ns for the SDA signal (referred to the VIH,MIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 11: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instance. Note 12: CB is total capacitance of one bus line in pF. ELECTRICAL CHARACTERISTICS (I2C INTERFACE) (2.5V < VBATT < 4.5V, TA = -20NC to +70NC, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency fSCL (Note 7) 0 400 kHz Bus Free Time Between a STOP and START Condition tBUF 1.3 F s START Condition (Repeated) Hold Time tHD:STA (Note 8) 0.6 F s Low Period of SCL Clock tLOW 1.3 F s High Period of SCL Clock tHIGH 0.6 F s Setup Time for a Repeated START Condition tSU:STA 0.6 F s Data Hold Time tHD:DAT (Notes 9, 10) 0 0.9 F s Data Setup Time tSU:DAT (Note 9) 100 ns Rise Time of Both SDA and SCL Signals tR 20 + 0.1CB 300 ns Fall Time of Both SDA and SCL Signals tF 20 + 0.1CB 300 ns Setup Time for STOP Condition tSU:STO 0.6 F s Spike Pulse Widths Suppressed by Input Filter tSP (Note 11) 0 50 ns Capacitive Load for Each Bus Line CB (Note 12) 400 pF SCL, SDA Input Capacitance CB,IN 60 pF |
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