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MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

TIMING CHARACTERISTICS

TIMING CHARACTERISTICS

Note 3: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated.

Note 4: Offset and reference errors nulled.

Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.

Note 6: Defined as the change in positive full scale caused by a Q5% variation in the nominal supply voltage.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Acquisition Time

1.1

F

s

SCLK to DOUT Valid

50

ns

CS Fall to DOUT Enable

80

ns

CS Rise to DOUT Disable

80

ns

CS Pulse Width

50

ns

CS Fall to SCLK Rise Setup

100

ns

CS Rise to SCLK Rise Hold

0

ns

SCLK High Pulse Width

65

ns

SCLK Low Pulse Width

65

ns

SCLK Period

208

ns

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Acquisition Time

1.1

F

s

SCLK to DOUT Valid

100

ns

CS Fall to DOUT Enable

100

ns

CS Rise to DOUT Disable

80

ns

CS Pulse Width

50

ns

CS Fall to SCLK Rise Setup

100

ns

CS Rise to SCLK Rise Hold

0

ns

SCLK High Pulse Width

65

ns

SCLK Low Pulse Width

65

ns

SCLK Period

208

ns