����������������������������������������������������������������� Maxim Integrated Products 9

MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

Detailed Description

The MAX11100 includes an input track-and-hold (T/H)

and successive-approximation register (SAR) circuitry to

convert an analog input signal to a digital 16-bit output.

Figure 4 shows the MAX11100 in its simplest configura-

tion. The serial interface requires only three digital lines

(SCLK, CS, and DOUT) and provides an easy interface

to microprocessors (FPs).

The MAX11100 has two power modes: normal and shut-

down. Driving CS high places the MAX11100 in shut-

down, reducing the supply current to 0.1FA (typ), while

pulling CS low places the MAX11100 in normal operating

mode. Falling edges on CS initiate conversions that are

driven by SCLK. The conversion result is available at

DOUT in unipolar serial format. The serial data stream

consists of eight zeros followed by the data bits (MSB

first). Figure 3 shows the interface timing diagram.

Analog Input

Figure 5 illustrates the input sampling architecture of the

ADC. The voltage applied at REF sets the full-scale input

voltage.

Track-and-Hold (T/H)

In track mode, the analog signal is acquired on the inter-

nal hold capacitor. In hold mode, the T/H switches open

and the capacitive DAC samples the analog input.

Figure 1. Load Circuits for DOUT Enable Time and SCLK to

DOUT Delay Time

Figure 2. Load Circuits for DOUT Disable Time

Figure 3. Detailed Serial Interface Timing

DOUT

DOUT

1mA

1mA

DGND

DGND

DOUT

DOUT

1mA

1mA

DGND

DGND

SCLK

DOUT

CS