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HYS72V32220GU-8B Datasheet(PDF) 11 Page - Siemens Semiconductor Group |
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HYS72V32220GU-8B Datasheet(HTML) 11 Page - Siemens Semiconductor Group |
11 / 17 page HYS 64(72)V16200/3222(0)0/64220GU SDRAM Modules Semiconductor Group 11 1998-08-01 Notes 1. An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 2. AC timing tests have V IL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between V IH and VIL. All AC measurements assume t T = 1 ns with the AC output load circuit show. Specified tAC and tOH parameters are measured with a 50 pF only, without any resisitve termination and with a input signal of 1 V/ns edge rate between 0.8 V and 2.0 V. 3. If clock rising time is longer than 1 ns, a time ( t T/2 – 0.5) ns has to be added to this parameter. 4. Rated at 1.5 V 5. If t T is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter. 6. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device. 7. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to t RC is satisfied once the Self Refresh Exit command is registered. 8. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. SPT03404 CLOCK 2.4 V 0.4 V INPUT HOLD t SETUP t t T OUTPUT 1.4 V t LZ AC t t AC OH t HZ t 1.4 V CL t CH t 50 pF I/O Measurement conditions for t AC and tOH |
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