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AK8859VQ Datasheet(PDF) 3 Page - Asahi Kasei Microsystems |
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AK8859VQ Datasheet(HTML) 3 Page - Asahi Kasei Microsystems |
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3 / 73 page  [AK8859VQ] MS1178-E-00 AKM Confidential 2010/04 - 3 - [7.22.2] Output timing signal diagram.............................................................................................. 32 [7.23] Digital Pixel interpolator ............................................................................................................. 33 [7.24] Clock generation ......................................................................................................................... 34 [7.24.1.] Line-locked clock mode ...................................................................................................... 34 [7.24.2.] Frame-locked clock mode................................................................................................... 34 [7.24.3.] Fixed-clock mode................................................................................................................. 34 [7.24.4.] Auto transition mode........................................................................................................... 34 [7.25.] PGA (Programmable Gain Amp) ............................................................................................... 34 [7.26.] AGC (Auto Gain Control) ........................................................................................................... 35 [7.27.] ACC (Auto Color Control) .......................................................................................................... 36 [7.28.] Sharpness adjustment ............................................................................................................... 36 [7.29.] Color Killer .................................................................................................................................. 36 [7.30.] Image quality adjustment .......................................................................................................... 37 [7.30.1.] Contrast adjustment ............................................................................................................ 37 [7.30.2.] Brightness adjustment........................................................................................................ 37 [7.30.3.] Color saturation adjustment............................................................................................... 38 [7.30.4.] HUE adjustment ................................................................................................................... 38 [7.31.] VBI information decoding.......................................................................................................... 39 [7.32.] Internal status indicator............................................................................................................. 40 [7.32.1.] Input signal indicator........................................................................................................... 40 [7.32.2.] Status of VLOCK mechanism ............................................................................................. 40 [7.32.3.] Interlace signal indicator..................................................................................................... 40 [7.32.4.] Color killer operational........................................................................................................ 40 [7.32.5.] Clock mode........................................................................................................................... 40 [7.32.6.] Luminance decode overflow .............................................................................................. 40 [7.32.7.] Color decode overflow ........................................................................................................ 41 [7.32.8.] AGC status............................................................................................................................ 41 [7.33.] Macrovision signal detection .................................................................................................... 41 [7.34.] Auto detection result of input video signal ............................................................................. 42 [8.] Device control interface ..................................................................................................................... 43 [8.1.] I 2C bus SLAVE Address ............................................................................................................... 43 [8.2.] I 2C control sequence.................................................................................................................... 43 [8.2.1.] Write sequence ...................................................................................................................... 43 [8.2.2.] Read sequence....................................................................................................................... 43 [8.2.3.] I 2C General Call ...................................................................................................................... 43 [9.] Register definitions............................................................................................................................. 45 [9.1.] Register setting overview ............................................................................................................ 47 [9.1.1.] Sub Address 0x00 “Input Channel Select Register (R/W)”................................................ 47 [9.1.2.] Sub Address 0x01 “Clamp Control Register (R/W)” .......................................................... 48 [9.1.3.] Sub Address 0x02 “Input Video Standard Register (R/W)” ............................................... 49 [9.1.4.] Sub Address 0x03 “NDMODE Register (R/W)” ................................................................... 50 [9.1.5.] Sub Address 0x04 “Output Format Register (R/W)” .......................................................... 51 [9.1.6.] Sub Address 0x05 “Output Pin Control Register (R/W)” ................................................... 53 [9.1.7.] Sub Address 0x06 “Output Pin Polarity Set Register (R/W)”............................................ 54 [9.1.8.] Sub Address 0x07 “Control 0 Register (R/W)” ................................................................... 55 [9.1.9.] Sub Address 0x08 “Control 1 Register (R/W)” ................................................................... 56 [9.1.10.] Sub Address 0x09 “Reserved Register (R/W)” ................................................................. 56 [9.1.11.] Sub Address 0x0A “PGA1 Control Register (R/W)” ......................................................... 57 [9.1.12.] Sub Address 0x0B “PGA2 Control Register (R/W)” ......................................................... 57 [9.1.13.] Sub Address 0x0C “AGC and Color Control Register (R/W)”......................................... 58 [9.1.14.] Sub Address 0x0D “Contrast Control Register (R/W)” .................................................... 59 |
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