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AK5357 Datasheet(PDF) 8 Page - Asahi Kasei Microsystems |
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AK5357 Datasheet(HTML) 8 Page - Asahi Kasei Microsystems |
8 / 20 page [AK5357] MS0294-E-03 200 9/03 - 8 - SWITCHING CHARACTERISTICS (Ta=Tmin ∼ Tmax; VA=VD=2.7 ∼ 5.5V; CL=20pF) Parameter Symbol min typ max Units Master Clock Timing Frequency Pulse Width Low Pulse Width High fCLK tCLKL tCLKH 1.024 0.4/fCLK 0.4/fCLK 36.864 MHz ns ns LRCK Frequency fs 4 96 kHz Duty Cycle Slave mode Master mode 45 50 55 % % Audio Interface Timing Slave mode SCLK Period SCLK Pulse Width Low Pulse Width High LRCK Edge to SCLK “ ↑” (Note 11) SCLK “ ↑” to LRCK Edge (Note 11) LRCK to SDTO (MSB) (Except I2S mode) SCLK “ ↓” to SDTO tSCK tSCKL tSCKH tLRSH tSHLR tLRS tSSD 160 65 65 30 30 35 35 ns ns ns ns ns ns ns Master mode SCLK Frequency SCLK Duty SCLK “ ↓” to LRCK SCLK “ ↓” to SDTO fSCK dSCK tMSLR tSSD −20 −20 64fs 50 20 35 Hz % ns ns Reset Timing PDN Pulse Width (Note 12) PDN “ ↑” to SDTO valid at Slave Mode (Note 13) PDN “ ↑” to SDTO valid at Master Mode (Note 13) tPD tPDV tPDV 150 4132 4129 ns 1/fs 1/fs Note 11. SCLK rising edge must not occur at the same time as LRCK edge. Note 12. The AK5357 can be reset by bringing the PDN pin = “L”. Note 13. This cycle is the number of LRCK rising edges from the PDN pin = “H”. |
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