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AK4686 Datasheet(PDF) 10 Page - Asahi Kasei Microsystems |
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AK4686 Datasheet(HTML) 10 Page - Asahi Kasei Microsystems |
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10 / 39 page  [AK4686] MS1243-E-01 2010/10 - 10 - Parameter Symbol min typ max Units Audio Interface Timing (Slave Mode) PORT1(DAC1), PORT2 (DAC2) BICK1, 2 Period BICK1, 2 Pulse Width Low Pulse Width High LRCK1, 2 Edge to BICK1, 2 “ ↑” (Note 11) BICK1, 2 “ ↑” to LRCK1, 2 Edge (Note 11) SDTI1, 2 Hold Time SDTI1, 2 Setup Time tBCK tBCKL tBCKH tLRB tBLR tSDH tSDS 81 32 32 20 20 10 10 ns ns ns ns ns ns ns PORT1 (ADC) BICK1 Period BICK1 Pulse Width Low Pulse Width High LRCK1 Edge to BICK1 “ ↑” (Note 11) BICK1 “ ↑” to LRCK1 Edge (Note 11) LRCK1 to SDTO1 (MSB) BICK1 “ ↓” to SDTO1 tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD 324 128 128 80 80 80 80 ns ns ns ns ns ns ns Audio Interface Timing (Master Mode) BICK1 Frequency BICK1 Duty BICK1 “ ↓” to LRCK1 Edge BICK1 “ ↓” to SDTO1 SDTI1 Hold Time SDTI1 Setup Time fBCK dBCK tMBLR tBSD tSDH tSDS -20 25 10 64fs 50 20 20 Hz % ns ns ns ns Control Interface Timing (I2C Bus): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 12) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Capacitive load on bus fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP Cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 - 0 400 - - - - - - - 0.3 0.3 - 50 400 kHz μs μs μs μs μs μs μs μs μs μs ns pF Note 11. BICK rising edge must not occur at the same time as LRCK edge. Note 12. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 13. I2C-bus is a trademark of NXP B.V. |
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