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AK4636 Datasheet(PDF) 11 Page - Asahi Kasei Microsystems |
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AK4636 Datasheet(HTML) 11 Page - Asahi Kasei Microsystems |
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11 / 105 page  [AK4636] MS1012-E-01 2010/08 - 11 - Parameter min typ max Units Power Supplies Power Up (PDN = “H”) All Circuit Power-up: (Note 15) AVDD+DVDD fs=8kHz (LP bit = “1”) (Note 17) - 7 - mA fs=48kHz(LP bit = “0”) (Note 17) - 11 17 mA SVDD: Speaker-Amp Normal Operation (SPPSN bit = “1”, No Output) - 4 12 mA VVDD (Note 16) - 8 12 mA Power Down (PDN = “L”) (Note 18) AVDD+DVDD+SVDD+VVDD - 1 5 μA Note 7. The voltage difference between MICP and MICN pins. AC coupling capacitor should be inserted in series at each input pin. Full-differential microphone input is not available at MGAIN3-0 bits = “1000” or “0000”. If the input signal over those maximum voltages are input, the ADC does not operate properly. Note 8. When a PLL reference clock is input to the FCK pin in PLL Slave Mode, S/ (N+D) of MIC ADC is 75dB (typ), S/ (N+D) of DAC AOUT is75dB (typ). Note 9. When LOVL bit = “1”, large-amplitude output may have clip noise. Note 10. When SPGK1-0 bits = “01” or “10”, large-amplitude output may have clip noise if the SVDD is low. Note 11. The maximum input voltage is inversely proportional to the external input resistance (Rin). Vout = Vin × Rin/33k Ω(max). The volume can not be changed by BPLVL 7-0 bits in “BEEP pin External Input Resistance Mode” (BPM1-0 bits = “10”). BPLVL 7-0 bits should be fixed “00H” to change the gain by the external resistance (Rin). Note 12. Input Voltage does not depend on VVDD voltage. Note 13. Measurement point is A of Figure 2. Note 14. This is the value when the lowest input signal level is more than -20IRE. Note 15. When PLL Master Mode (MCKI=12MHz), and PMV = PMMP = PMADC = PMDAC = PMPFIL = PMSPK = PMVCM = PMPLL = MCKO = PMAO = M/S = “1”. The MPI pin outputs 0mA. In EXT mode, when PMPLL= MCKO= M/S= “0” and LP= “0”, AVDD+ DVDD= 6mA (fs=8kHz, typ) or 9mA (fs=48kHz, typ), when LP= “1”, AVDD+DVDD = 5mA (fs=8kHz, typ). Note 16. When Black signal is input to the VIN pin, and the VOUT pin has no load resistance. If the resistance is 150 Ω, it is 12.5mA(typ). Note 17. Set LP bit = “1” when sampling frequency ≤ 22.05kHz, set LP bit = “0” when > 22.05kHz. Note 18. All digital input pins are fixed to DVDD or VSS2. VIN VOUT CLAMP 75 Ω LPF GCA +6dB Measuring point A 75 Ω -1dB ~ +10.5dB St ep 0. 5dB Figure 2. Measurement Point |
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