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Q67100-Q2185 Datasheet(PDF) 1 Page - Siemens Semiconductor Group |
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Q67100-Q2185 Datasheet(HTML) 1 Page - Siemens Semiconductor Group |
1 / 17 page Semiconductor Group 1 3.3V 4M × 64-Bit EDO-DRAM Module 3.3V 4M x 72-Bit EDO-DRAM Module 168pin unbuffered DIMM Module with serial presence detect HYM64V4005GU-50/-60 HYM64V4045GU-50/-60 HYM72V4005GU-50/-60 HYM72V4045GU-50/-60 • 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual In-Line Memory Module for PC main memory applications • 1 bank 4M x 64, 4M x 72 in 2k and 4k refresh organisations • Optimized for byte-write non-parity or ECC applications • Extended Data Out (EDO) • Performance: • Single +3.3 V ± 0.3 V Power Supply • CAS-before-RAS refresh, RAS-only-refresh • Decoupling capacitors mounted on substrate • All inputs, outputs and clocks are fully LV-TTL compatible • Serial presence detects (optional) • Utilizes 4M x 4 -DRAMs in TSOPII packages • 2048 refresh cycles / 32 ms with 11 / 11 addressing ( Row / Column) for HYM64/72V4005GU • 4096 refresh cycles / 64 ms with 12 / 10 addressing ( Row / Column) for HYM64/72V4045GU • Gold contact pads • Card Size: 133,35mm x 25,40 mm x 4,00 mm • This DRAM product module family is intended to be fully pin and architecture compatible with the 168pin unbuffered SDRAM DIMM module family -50 -60 tRAC RAS Access Time 50 ns 60 ns tCAC CAS Access Time 13 ns 15 ns tAA Access Time from Address 25 ns 30 ns tRC Cycle Time 84 ns 104 ns tHPC EDO Mode Cycle Time 20 ns 25 ns 1 2.97 |
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