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MAX5725AWP+T Datasheet(PDF) 7 Page - Maxim Integrated Products

Part # MAX5725AWP+T
Description  Ultra-Small, Octal-Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and SPI Interface
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX5725AWP+T Datasheet(HTML) 7 Page - Maxim Integrated Products

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Ultra-Small, Octal-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and SPI Interface
MAX5723/MAX5724/MAX5725
 Maxim Integrated Products 7
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SPI TIMING CHARACTERISTICS
SCLK Frequency
fSCLK
2.7V < VDDIO < 5.5V
Write mode
0
50
MHz
Read mode,
strobing on 1 SCLK
0
25
Read mode,
strobing on ½ SCLK
0
12.5
1.8V < VDDIO < 2.7V
Write mode
0
33
Read mode,
strobing on 1 SCLK
0
20
Read mode,
strobing on ½ SCLK
0
10
SCLK Period
tSCLK
2.7V < VDDIO < 5.5V, write mode
20
ns
1.8V < VDDIO < 2.7V, write mode
30
SCLK Pulse Width High
tCH
8
ns
SCLK Pulse Width Low
tCL
8
ns
CSB Fall to SCLK Fall Setup Time
tCSS0
To first SCLK falling
edge
2
.7V < VDDIO < 5.5V
8
ns
1.8V < VDDIO < 2.7V
12
CSB Fall to SCLK Fall Hold Time
tCSH0
Applies to inactive SCLK falling edge
preceding the first SCLK falling edge
0
ns
CSB Rise to SCLK Fall Hold Time
tCSH1
Applies to the 24
th SCLK falling edge
0
ns
CSB Rise to SCLK Fall
tCSA
Applies to the 24
th SCLK falling edge,
aborted sequence
12
ns
SCLK Fall to CSB Fall
tCSF
A
pplies to 24th SCLK falling edge
100
ns
CSB Pulse Width High
tCSPW
20
ns
DIN to SCLK Fall Setup Time
tDS
5
ns
DIN to SCLK Fall Hold Time
tDH
4.5
ns
CLR Pulse Width Low
tCLPW
20
ns
CLR Rise to CSB Fall
tCSC
Required for command to be executed
20
ns
LDAC Pulse Width Low
tLDPW
20
ns
LDAC Fall to SCLK Fall Hold
tLDH
A
pplies to 24th SCLK falling edge
20
ns
SCLK Fall to DOUT Transition
tDOT
DPHA = 0,
CLOAD = 20pF
2
.7V < VDDIO < 5.5V
35
ns
1.8V < VDDIO < 2.7V
40
SCLK Rise to DOUT Transition
tDOT
DPHA = 1,
CLOAD = 20pF
2
.7V < VDDIO < 5.5V
35
ns
1.8V < VDDIO < 2.7V
40


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