MCM6265C

1

MOTOROLA FAST SRAM

8K x 9 Bit Fast Static RAM

The MCM6265C is fabricated using Motorola’s high–performance silicon–gate

CMOS technology. Static design eliminates the need for external clocks or timing

strobes, while CMOS circuitry reduces power consumption and provides for

greater reliability.

This device meets JEDEC standards for functionality and pinout, and is avail-

able in plastic dual–in–line and plastic small–outline J–leaded packages.

• Single 5 V ± 10% Power Supply

• Fully Static — No Clock or Timing Strobes Necessary

• Fast Access Times: 12, 15, 20, 25, and 35 ns

• Equal Address and Chip Enable Access Times

• Output Enable (G) Feature for Increased System Flexibility and to

Eliminate Bus Contention Problems

• Low Power Operation: 110 – 150 mA Maximum AC

• Fully TTL Compatible — Three State Output

ROW

DECODER

MEMORY MATRIX

256 ROWS x 32

x 9 COLUMNS

INPUT

DATA

CONTROL

COLUMN I/O

COLUMN DECODER

DQ0

E1

W

VCC

VSS

A1

DQ8

G

BLOCK DIAGRAM

E2

A0

A6

A8 A12

A11

A10

A9

A7

A5

A4

A3

A2

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by MCM6265C/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

PIN ASSIGNMENT

MCM6265C

P PACKAGE

300 MIL PLASTIC

CASE 710B–01

A0 – A12

Address Input

. . . . . . . . . . . . .

DQ0 – DQ8

Data Input/Data Output

. . .

W

Write Enable

. . . . . . . . . . . . . . . . . . . .

G

Output Enable

. . . . . . . . . . . . . . . . . . .

E1, E2

Chip Enable

. . . . . . . . . . . . . . . . .

VCC

Power Supply (+ 5 V)

. . . . . . . . . . .

VSS

Ground

. . . . . . . . . . . . . . . . . . . . . . .

PIN NAMES

J PACKAGE

300 MIL SOJ

CASE 810B–03

5

4

3

2

1

10

9

8

7

6

11

12

13

14

20

21

22

23

24

25

26

19

27

28

18

17

16

15

A2

A5

A6

A7

A8

DQ1

A1

A4

VSS

DQ3

DQ2

A3

A0

DQ0

A10

A9

E2

W

VCC

DQ5

DQ6

DQ7

DQ4

E1

G

A11

DQ8

A12

REV 2

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